ASoC: rt5677: add i2s asrc clk src selection
authorBard Liao <bardliao@realtek.com>
Tue, 28 Apr 2015 03:27:40 +0000 (11:27 +0800)
committerMark Brown <broonie@kernel.org>
Wed, 29 Apr 2015 11:20:26 +0000 (12:20 +0100)
The ASRC source of i2s are also configurable. We add the selection
in the existing rt5677_sel_asrc_clk_src API.

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/rt5677.c
sound/soc/codecs/rt5677.h

index af182586712d42f9bbac6d5b03338e3e5219cf23..331e638b28f4f330f49ddd6d72d38fcc236827b4 100644 (file)
@@ -1057,6 +1057,7 @@ int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
        unsigned int asrc5_mask = 0, asrc5_value = 0;
        unsigned int asrc6_mask = 0, asrc6_value = 0;
        unsigned int asrc7_mask = 0, asrc7_value = 0;
+       unsigned int asrc8_mask = 0, asrc8_value = 0;
 
        switch (clk_src) {
        case RT5677_CLK_SEL_SYS:
@@ -1193,6 +1194,35 @@ int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
                        asrc7_value);
 
+       /* ASRC 8 */
+       if (filter_mask & RT5677_I2S1_SOURCE) {
+               asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
+               asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
+                       | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
+       }
+
+       if (filter_mask & RT5677_I2S2_SOURCE) {
+               asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
+               asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
+                       | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
+       }
+
+       if (filter_mask & RT5677_I2S3_SOURCE) {
+               asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
+               asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
+                       | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
+       }
+
+       if (filter_mask & RT5677_I2S4_SOURCE) {
+               asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
+               asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
+                       | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
+       }
+
+       if (asrc8_mask)
+               regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
+                       asrc8_value);
+
        return 0;
 }
 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
index 9dceb41d18ea910db762dd69b7aa4506632ae1a5..62571d071a8d69af8e2c988c3ee5b88666debb23 100644 (file)
 #define RT5677_DSP_OB_4_7_CLK_SEL_MASK         (0xf << 8)
 #define RT5677_DSP_OB_4_7_CLK_SEL_SFT          8
 
+/* ASRC Control 8 (0x8a) */
+#define RT5677_I2S1_CLK_SEL_MASK               (0xf << 12)
+#define RT5677_I2S1_CLK_SEL_SFT                        12
+#define RT5677_I2S2_CLK_SEL_MASK               (0xf << 8)
+#define RT5677_I2S2_CLK_SEL_SFT                        8
+#define RT5677_I2S3_CLK_SEL_MASK               (0xf << 4)
+#define RT5677_I2S3_CLK_SEL_SFT                        4
+#define RT5677_I2S4_CLK_SEL_MASK               (0xf)
+#define RT5677_I2S4_CLK_SEL_SFT                        0
+
 /* VAD Function Control 4 (0x9f) */
 #define RT5677_VAD_SRC_MASK                    (0x7 << 8)
 #define RT5677_VAD_SRC_SFT                     8
@@ -1744,6 +1754,10 @@ enum {
        RT5677_AD_MONO_R_FILTER = (0x1 << 12),
        RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),
        RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),
+       RT5677_I2S1_SOURCE = (0x1 << 15),
+       RT5677_I2S2_SOURCE = (0x1 << 16),
+       RT5677_I2S3_SOURCE = (0x1 << 17),
+       RT5677_I2S4_SOURCE = (0x1 << 18),
 };
 
 struct rt5677_priv {