RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 0bc86e5f8f3fbbb0832a838a98af3a694bbf66b5..cb35ffd8ec6be590ef965a946d1b89f78b09eda8 100644 (file)
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 {
        this_leaf->level = level;
        this_leaf->type = type;
-       /* not a sector cache */
-       this_leaf->physical_line_partition = 1;
-       /* TODO: Add to DTS */
-       this_leaf->attributes =
-               CACHE_WRITE_BACK
-               | CACHE_READ_ALLOCATE
-               | CACHE_WRITE_ALLOCATE;
 }
 
 static int __init_cache_level(unsigned int cpu)