PCI: dwc: all: Rename cfg_read/cfg_write to read/write

No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
anything specific to access configuration space. It can be just renamed to
dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Joao Pinto <jpinto@synopsys.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index d1cd476dee9f15e7767b0689faa24146f3cdcbc5..4b9b1e1f00cb8a728af8cabf275c48104d02d380 100644 (file)
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -109,22 +109,22 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
        }
 
        if (dra7xx->link_gen == 1) {
-               dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
-                                4, &reg);
+               dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
+                            4, &reg);
                if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
                        reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
                        reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
-                       dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
-                                         PCI_EXP_LNKCAP, 4, reg);
+                       dw_pcie_write(pp->dbi_base + exp_cap_off +
+                                     PCI_EXP_LNKCAP, 4, reg);
                }
 
-               dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
-                                2, &reg);
+               dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
+                            2, &reg);
                if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
                        reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
                        reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
-                       dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
-                                         PCI_EXP_LNKCTL2, 2, reg);
+                       dw_pcie_write(pp->dbi_base + exp_cap_off +
+                                     PCI_EXP_LNKCTL2, 2, reg);
                }
        }
 

diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index c179e7aaeedbf300780fa1fea6da169e30ba8f12..e3fbff4d6de77fa9bc82e6bfc8c6e966fe421d61 100644 (file)
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -429,7 +429,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
        int ret;
 
        exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
-       ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+       ret = dw_pcie_read(pp->dbi_base + where, size, val);
        exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
        return ret;
 }
@@ -441,7 +441,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
        int ret;
 
        exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
-       ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
+       ret = dw_pcie_write(pp->dbi_base + where, size, val);
        exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
        return ret;
 }

diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 9397c46671062b011e6a6f9f523f9d2d0b95c1c4..48753345adc784199a799d43fb2cf884a304ed91 100644 (file)
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -444,7 +444,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
        addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 
-       return dw_pcie_cfg_read(addr + where, size, val);
+       return dw_pcie_read(addr + where, size, val);
 }
 
 int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -456,7 +456,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
        addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 
-       return dw_pcie_cfg_write(addr + where, size, val);
+       return dw_pcie_write(addr + where, size, val);
 }
 
 /**

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index d0e49041dd0a190387a80f930fbaf9dcbd8f656e..de143ea5f28c31f1414169ea19910ad81dbbfbd3 100644 (file)
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -33,7 +33,7 @@
 
 static struct pci_ops dw_pcie_ops;
 
-int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
+int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
        if ((uintptr_t)addr & (size - 1)) {
                *val = 0;
@@ -54,7 +54,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
        return PCIBIOS_SUCCESSFUL;
 }
 
-int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
+int dw_pcie_write(void __iomem *addr, int size, u32 val)
 {
        if ((uintptr_t)addr & (size - 1))
                return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -108,7 +108,7 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
        if (pp->ops->rd_own_conf)
                return pp->ops->rd_own_conf(pp, where, size, val);
 
-       return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+       return dw_pcie_read(pp->dbi_base + where, size, val);
 }
 
 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
@@ -117,7 +117,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
        if (pp->ops->wr_own_conf)
                return pp->ops->wr_own_conf(pp, where, size, val);
 
-       return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
+       return dw_pcie_write(pp->dbi_base + where, size, val);
 }
 
 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
@@ -635,7 +635,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
        dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
                                  type, cpu_addr,
                                  busdev, cfg_size);
-       ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
+       ret = dw_pcie_read(va_cfg_base + where, size, val);
        if (pp->num_viewport <= 2)
                dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
                                          PCIE_ATU_TYPE_IO, pp->io_base,
@@ -673,7 +673,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
        dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
                                  type, cpu_addr,
                                  busdev, cfg_size);
-       ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
+       ret = dw_pcie_write(va_cfg_base + where, size, val);
        if (pp->num_viewport <= 2)
                dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
                                          PCIE_ATU_TYPE_IO, pp->io_base,

diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b5226d471d523aab8f2b12a1e1c2a2d4a90aa1a7..5b71b5772dc6119622a043880bc70f0d8b6845b2 100644 (file)
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -145,8 +145,8 @@ struct pcie_host_ops {
 
 u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg);
 void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val);
-int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
-int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
+int dw_pcie_read(void __iomem *addr, int size, u32 *val);
+int dw_pcie_write(void __iomem *addr, int size, u32 val);
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_wait_for_link(struct pcie_port *pp);

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 3f525cb985ee457506894e67fba64a18e4ac9d42..ac27b67d303e3701d5d8f1fae33db57b9763c3ca 100644 (file)
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -621,7 +621,7 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
                return PCIBIOS_SUCCESSFUL;
        }
 
-       return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+       return dw_pcie_read(pp->dbi_base + where, size, val);
 }
 
 static struct pcie_host_ops qcom_pcie_dw_ops = {

diff --git a/drivers/pci/dwc/pcie-spear13xx.c b/drivers/pci/dwc/pcie-spear13xx.c
index 59705661cc975d062925f113ee0783050445f419..7acf91e07f5d13a581e6eb94eda8ed2adb4e5fa2 100644 (file)
--- a/drivers/pci/dwc/pcie-spear13xx.c
+++ b/drivers/pci/dwc/pcie-spear13xx.c
@@ -91,34 +91,34 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
         * default value in capability register is 512 bytes. So force
         * it to 128 here.
         */
-       dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
+       dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
        val &= ~PCI_EXP_DEVCTL_READRQ;
-       dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
+       dw_pcie_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
 
-       dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
-       dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
+       dw_pcie_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
+       dw_pcie_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
 
        /*
         * if is_gen1 is set then handle it, so that some buggy card
         * also works
         */
        if (spear13xx_pcie->is_gen1) {
-               dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
-                                       4, &val);
+               dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
+                            4, &val);
                if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
                        val &= ~((u32)PCI_EXP_LNKCAP_SLS);
                        val |= PCI_EXP_LNKCAP_SLS_2_5GB;
-                       dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
-                               PCI_EXP_LNKCAP, 4, val);
+                       dw_pcie_write(pp->dbi_base + exp_cap_off +
+                                     PCI_EXP_LNKCAP, 4, val);
                }
 
-               dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
-                                       2, &val);
+               dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
+                            2, &val);
                if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
                        val &= ~((u32)PCI_EXP_LNKCAP_SLS);
                        val |= PCI_EXP_LNKCAP_SLS_2_5GB;
-                       dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
-                                       PCI_EXP_LNKCTL2, 2, val);
+                       dw_pcie_write(pp->dbi_base + exp_cap_off +
+                                     PCI_EXP_LNKCTL2, 2, val);
                }
        }