drm/amd/display: Expose configure_encoder for link_encoder

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index fd9dc70190a88b26a8d5424fc8bb3a1b03aaea6d..18a7cac4f6e31b30af1777b47c6db626747db1ce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -445,12 +445,11 @@ static uint8_t get_frontend_source(
        }
 }
 
-static void configure_encoder(
+void configure_encoder(
        struct dcn10_link_encoder *enc10,
        const struct dc_link_settings *link_settings)
 {
        /* set number of lanes */
-
        REG_SET(DP_CONFIG, 0,
                        DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index d8ef30bed9ff68e9171578dd90f146055d87bd51..cd3bb5d40579c38aff03011653bfac8c0a030f49 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -271,6 +271,10 @@ void dcn10_link_encoder_setup(
        struct link_encoder *enc,
        enum signal_type signal);
 
+void configure_encoder(
+       struct dcn10_link_encoder *enc10,
+       const struct dc_link_settings *link_settings);
+
 /* enables TMDS PHY output */
 /* TODO: still need depth or just pass in adjusted pixel clock? */
 void dcn10_link_encoder_enable_tmds_output(