ARM: OMAP: hwmod: align the SmartReflex fck names

Rename the smartreflex fck names for consistency and better readability;
rename the clock aliases so that they match the hwmod main_clk names.

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>

diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 114ab4b8e0e356883192bb847237172df9d46ab3..0bf5458b72f995481ad174ad806e7b4ec8f95f7a 100644 (file)
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -548,16 +548,16 @@ static struct clk mcasp1_fck = {
        .recalc         = &followparent_recalc,
 };
 
-static struct clk smartreflex0_fck = {
-       .name           = "smartreflex0_fck",
+static struct clk smartreflex_mpu_fck = {
+       .name           = "smartreflex_mpu_fck",
        .clkdm_name     = "l4_wkup_clkdm",
        .parent         = &sys_clkin_ck,
        .ops            = &clkops_null,
        .recalc         = &followparent_recalc,
 };
 
-static struct clk smartreflex1_fck = {
-       .name           = "smartreflex1_fck",
+static struct clk smartreflex_core_fck = {
+       .name           = "smartreflex_core_fck",
        .clkdm_name     = "l4_wkup_clkdm",
        .parent         = &sys_clkin_ck,
        .ops            = &clkops_null,
@@ -1039,8 +1039,8 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
        CLK("NULL",     "mmc2_fck",             &mmc2_fck,      CK_AM33XX),
        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
-       CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
-       CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
+       CLK(NULL,       "smartreflex_mpu_fck",  &smartreflex_mpu_fck,   CK_AM33XX),
+       CLK(NULL,       "smartreflex_core_fck", &smartreflex_core_fck,  CK_AM33XX),
        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1f42c9d5ecf3131b5f55fd6d2152912d44b2d9ff..d1786fca6919c55422e11c9d8f808aea7267f8d3 100644 (file)
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3050,8 +3050,8 @@ static struct clk traceclk_fck = {
 /* SR clocks */
 
 /* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
-       .name           = "sr1_fck",
+static struct clk smartreflex_mpu_iva_fck = {
+       .name           = "smartreflex_mpu_iva_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &sys_ck,
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3061,8 +3061,8 @@ static struct clk sr1_fck = {
 };
 
 /* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
-       .name           = "sr2_fck",
+static struct clk smartreflex_core_fck = {
+       .name           = "smartreflex_core_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &sys_ck,
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3478,8 +3478,8 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
-       CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
-       CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
+       CLK(NULL,       "smartreflex_mpu_iva_fck",      &smartreflex_mpu_iva_fck,       CK_34XX | CK_36XX),
+       CLK(NULL,       "smartreflex_core_fck", &smartreflex_core_fck,  CK_34XX | CK_36XX),
        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d661d138f27057d2dcc2130d741f6c0fa53bcb9d..35e943fb1a36144d4b7058f1860c992c6feecfd7 100644 (file)
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3226,9 +3226,9 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
        CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
-       CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
-       CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
-       CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
+       CLK(NULL,       "smartreflex_core_fck", &smartreflex_core_fck,  CK_443X),
+       CLK(NULL,       "smartreflex_iva_fck",  &smartreflex_iva_fck,   CK_443X),
+       CLK(NULL,       "smartreflex_mpu_fck",  &smartreflex_mpu_fck,   CK_443X),
        CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
        CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
        CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f67b7ee07dd4f5575e206c2098bb67c88fa32873..9693a187ff66ce6bbca1712827ab83d7fc04f738 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1406,7 +1406,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
 static struct omap_hwmod omap34xx_sr1_hwmod = {
        .name           = "smartreflex_mpu_iva",
        .class          = &omap34xx_smartreflex_hwmod_class,
-       .main_clk       = "sr1_fck",
+       .main_clk       = "smartreflex_mpu_iva_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@ -1424,7 +1424,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
 static struct omap_hwmod omap36xx_sr1_hwmod = {
        .name           = "smartreflex_mpu_iva",
        .class          = &omap36xx_smartreflex_hwmod_class,
-       .main_clk       = "sr1_fck",
+       .main_clk       = "smartreflex_mpu_iva_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@ -1451,7 +1451,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
 static struct omap_hwmod omap34xx_sr2_hwmod = {
        .name           = "smartreflex_core",
        .class          = &omap34xx_smartreflex_hwmod_class,
-       .main_clk       = "sr2_fck",
+       .main_clk       = "smartreflex_core_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@ -1469,7 +1469,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
 static struct omap_hwmod omap36xx_sr2_hwmod = {
        .name           = "smartreflex_core",
        .class          = &omap36xx_smartreflex_hwmod_class,
-       .main_clk       = "sr2_fck",
+       .main_clk       = "smartreflex_core_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,