drm/amd/powerplay: move clockgating to after ungating power in pp for uvd/vce

Cannot set clockgating state before ungating power.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 2da548f6337e822d3eeae9783d1b37190aa07d8c..2028980f1ed4f5be9694ce8fed4abb32e94fe014 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -177,12 +177,12 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                cz_dpm_powerdown_uvd(hwmgr);
        } else {
                cz_dpm_powerup_uvd(hwmgr);
-               cgs_set_clockgating_state(hwmgr->device,
-                                               AMD_IP_BLOCK_TYPE_UVD,
-                                               AMD_PG_STATE_GATE);
                cgs_set_powergating_state(hwmgr->device,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_CG_STATE_UNGATE);
+               cgs_set_clockgating_state(hwmgr->device,
+                                               AMD_IP_BLOCK_TYPE_UVD,
+                                               AMD_PG_STATE_GATE);
                cz_dpm_update_uvd_dpm(hwmgr, false);
        }
 
@@ -211,14 +211,14 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
                        } else {
                                cz_dpm_powerup_vce(hwmgr);
                                cz_hwmgr->vce_power_gated = false;
-                               cgs_set_clockgating_state(
-                                                       hwmgr->device,
-                                                       AMD_IP_BLOCK_TYPE_VCE,
-                                                       AMD_PG_STATE_GATE);
                                cgs_set_powergating_state(
                                                        hwmgr->device,
                                                        AMD_IP_BLOCK_TYPE_VCE,
                                                        AMD_CG_STATE_UNGATE);
+                               cgs_set_clockgating_state(
+                                                       hwmgr->device,
+                                                       AMD_IP_BLOCK_TYPE_VCE,
+                                                       AMD_PG_STATE_GATE);
                                cz_dpm_update_vce_dpm(hwmgr);
                                cz_enable_disable_vce_dpm(hwmgr, true);
                                return 0;