drm/i915/gen9: Implement WaDisableDgMirrorFixInHalfSliceChicken5
authorNick Hoath <nicholas.hoath@intel.com>
Thu, 5 Feb 2015 10:47:19 +0000 (10:47 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 13 Feb 2015 22:28:08 +0000 (23:28 +0100)
Move WaDisableDgMirrorFixInHalfSliceChicken5 to gen9_init_workarounds

v2: Added stepping check

v3: Removed unused register bitmap

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
[danvet: Bikesheds.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_ringbuffer.c

index bebefe79f7ce162b058790cdc3e0ba19326e5b62..2b89aacdda905848518e9a656faf205cf292c994 100644 (file)
@@ -63,14 +63,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
-       /*
-        * WaDisableDgMirrorFixInHalfSliceChicken5:skl
-        * This is a pre-production w/a.
-        */
-       I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
-                  I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
-                  ~GEN9_DG_MIRROR_FIX_ENABLE);
-
        /* Wa4x4STCOptimizationDisable:skl */
        I915_WRITE(CACHE_MODE_1,
                   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
index b869f1c687536d7b5e9974739c8bf83fc0256570..248db5157e0296a660545176938231665c83da06 100644 (file)
@@ -882,6 +882,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
+       if (INTEL_REVID(dev) == SKL_REVID_A0) {
+               /*
+               * WaDisableDgMirrorFixInHalfSliceChicken5:skl
+               * This is a pre-production w/a.
+               */
+               I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
+                       I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
+                       ~GEN9_DG_MIRROR_FIX_ENABLE);
+       }
+
        return 0;
 }