PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256

The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed
over 8 controller registers, therefore the maximum number of MSI IRQs
can be changed to 256. The number of controllers can be calculated based
on the number of vectors used by the specific SoC driver.

Update the dwc host bridge driver maximum number of supported MSI
IRQs.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Niklas Cassel <niklas.cassel@axis.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 193a0fa7b70909fa5b78b00e31a7890b3a7f2453..550fdbb5c226272d0e5d5656015a09196cfce932 100644 (file)
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -76,11 +76,13 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
 /* MSI int handler */
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
-       u32 val;
        int i, pos, irq;
+       u32 val, num_ctrls;
        irqreturn_t ret = IRQ_NONE;
 
-       for (i = 0; i < MAX_MSI_CTRLS; i++) {
+       num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
+       for (i = 0; i < num_ctrls; i++) {
                dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
                                    &val);
                if (!val)
@@ -639,13 +641,15 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
 
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
-       u32 val, ctrl;
+       u32 val, ctrl, num_ctrls;
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
        dw_pcie_setup(pci);
 
+       num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
        /* Initialize IRQ Status array */
-       for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
+       for (ctrl = 0; ctrl < num_ctrls; ctrl++)
                dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4,
                                    &pp->irq_status[ctrl]);
        /* setup RC BARs */

diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 923f9565a385a55a80e4e50c591b3f608989b62d..fe811dbc12cf7c854e76704f2e52153527252b98 100644 (file)
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -107,13 +107,9 @@
 #define MSI_MESSAGE_DATA_32            0x58
 #define MSI_MESSAGE_DATA_64            0x5C
 
-/*
- * Maximum number of MSI IRQs can be 256 per controller. But keep
- * it 32 as of now. Probably we will never need more than 32. If needed,
- * then increment it in multiple of 32.
- */
-#define MAX_MSI_IRQS                   32
-#define MAX_MSI_CTRLS                  (MAX_MSI_IRQS / 32)
+#define MAX_MSI_IRQS                   256
+#define MAX_MSI_IRQS_PER_CTRL          32
+#define MAX_MSI_CTRLS                  (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
 #define MSI_DEF_NUM_VECTORS            32
 
 /* Maximum number of inbound/outbound iATUs */