e1000e: cosmetic move of #defines to the new 80003es2lan.h

Move #defines specific to the ESB2/82563 family of devices to the new
80003es2lan.h header file.  These defines can be used by other files in the
driver and moving them to the 80003es2lan-family-specific file makes it
clearer to which devices they are applicable.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index a00457abce69d07ac067d5910b2c3cd8e7b00ea7..e0991388664c9322a11449b994d62d4bc888ef63 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -32,69 +32,6 @@
 
 #include "e1000.h"
 
-#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL      0x00
-#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL       0x02
-#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL        0x10
-#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE         0x1F
-
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS   0x0008
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS   0x0800
-#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING  0x0010
-
-#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
-#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT  0x0000
-#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE                 0x2000
-
-#define E1000_KMRNCTRLSTA_OPMODE_MASK           0x000C
-#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO    0x0004
-
-#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
-#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN       0x00010000
-
-#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN      0x8
-#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN    0x9
-
-/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disab. */
-#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
-#define GG82563_PSCR_CROSSOVER_MODE_MDI                 0x0000 /* 00=Manual MDI */
-#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
-#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
-
-/* PHY Specific Control Register 2 (Page 0, Register 26) */
-#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
-                                               /* 1=Reverse Auto-Negotiation */
-
-/* MAC Specific Control Register (Page 2, Register 21) */
-/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
-#define GG82563_MSCR_TX_CLK_MASK                0x0007
-#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
-#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
-#define GG82563_MSCR_TX_CLK_1000MBPS_25                 0x0007
-
-#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
-
-/* DSP Distance Register (Page 5, Register 26) */
-#define GG82563_DSPD_CABLE_LENGTH               0x0007 /* 0 = <50M
-                                                          1 = 50-80M
-                                                          2 = 80-110M
-                                                          3 = 110-140M
-                                                          4 = >140M
-                                                       */
-
-/* Kumeran Mode Control Register (Page 193, Register 16) */
-#define GG82563_KMCR_PASS_FALSE_CARRIER                 0x0800
-
-/* Max number of times Kumeran read/write should be validated */
-#define GG82563_MAX_KMRN_RETRY  0x5
-
-/* Power Management Control Register (Page 193, Register 20) */
-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
-                                          /* 1=Enable SERDES Electrical Idle */
-
-/* In-Band Control Register (Page 194, Register 18) */
-#define GG82563_ICR_DIS_PADDING                         0x0010 /* Disable Padding */
-
 /* A table for the GG82563 cable length where the range is defined
  * with a lower bound at "index" and the upper bound at
  * "index + 5".

diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.h b/drivers/net/ethernet/intel/e1000e/80003es2lan.h
new file mode 100644 (file)
index 0000000..90d363b
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.h
@@ -0,0 +1,95 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2013 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _E1000E_80003ES2LAN_H_
+#define _E1000E_80003ES2LAN_H_
+
+#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL     0x00
+#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL      0x02
+#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL       0x10
+#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE        0x1F
+
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS  0x0008
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS  0x0800
+#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
+
+#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
+#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
+#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE                0x2000
+
+#define E1000_KMRNCTRLSTA_OPMODE_MASK          0x000C
+#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO   0x0004
+
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00    /* Gig Carry Extend Padding */
+#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN      0x00010000
+
+#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN     0x8
+#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN   0x9
+
+/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002  /* 1=Reversal Dis */
+#define GG82563_PSCR_CROSSOVER_MODE_MASK       0x0060
+#define GG82563_PSCR_CROSSOVER_MODE_MDI                0x0000  /* 00=Manual MDI */
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX       0x0020  /* 01=Manual MDIX */
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO       0x0060  /* 11=Auto crossover */
+
+/* PHY Specific Control Register 2 (Page 0, Register 26) */
+#define GG82563_PSCR2_REVERSE_AUTO_NEG         0x2000  /* 1=Reverse Auto-Neg */
+
+/* MAC Specific Control Register (Page 2, Register 21) */
+/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
+#define GG82563_MSCR_TX_CLK_MASK               0x0007
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5         0x0004
+#define GG82563_MSCR_TX_CLK_100MBPS_25         0x0005
+#define GG82563_MSCR_TX_CLK_1000MBPS_25                0x0007
+
+#define GG82563_MSCR_ASSERT_CRS_ON_TX          0x0010  /* 1=Assert */
+
+/* DSP Distance Register (Page 5, Register 26)
+ * 0 = <50M
+ * 1 = 50-80M
+ * 2 = 80-100M
+ * 3 = 110-140M
+ * 4 = >140M
+ */
+#define GG82563_DSPD_CABLE_LENGTH              0x0007
+
+/* Kumeran Mode Control Register (Page 193, Register 16) */
+#define GG82563_KMCR_PASS_FALSE_CARRIER                0x0800
+
+/* Max number of times Kumeran read/write should be validated */
+#define GG82563_MAX_KMRN_RETRY                 0x5
+
+/* Power Management Control Register (Page 193, Register 20) */
+/* 1=Enable SERDES Electrical Idle */
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE    0x0001
+
+/* In-Band Control Register (Page 194, Register 18) */
+#define GG82563_ICR_DIS_PADDING                        0x0010  /* Disable Padding */
+
+#endif

diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 6f94437d8c0e17a33cb30402c20c4797b98425c7..8a145f4687210e0201e7c77c5762004521a4efbe 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -1003,5 +1003,6 @@ struct e1000_hw {
 };
 
 #include "82571.h"
+#include "80003es2lan.h"
 
 #endif