format = vsp1_entity_get_pad_format(&brx->entity, config, fmt->pad);
*format = fmt->format;
- /* Reset the compose rectangle */
+ /* Reset the compose rectangle. */
if (fmt->pad != brx->entity.source_pad) {
struct v4l2_rect *compose;
compose->height = format->height;
}
- /* Propagate the format code to all pads */
+ /* Propagate the format code to all pads. */
if (fmt->pad == BRX_PAD_SINK(0)) {
unsigned int i;
platform_set_drvdata(pdev, vsp1);
- /* I/O and IRQ resources (clock managed by the clock PM domain) */
+ /* I/O and IRQ resources (clock managed by the clock PM domain). */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
vsp1->mmio = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(vsp1->mmio))
return ret;
}
- /* FCP (optional) */
+ /* FCP (optional). */
fcp_node = of_parse_phandle(pdev->dev.of_node, "renesas,fcp", 0);
if (fcp_node) {
vsp1->fcp = rcar_fcp_get(fcp_node);
dev_dbg(&pdev->dev, "IP version 0x%08x\n", vsp1->version);
- /* Instanciate entities */
+ /* Instantiate entities. */
ret = vsp1_create_entities(vsp1);
if (ret < 0) {
dev_err(&pdev->dev, "failed to create entities\n");
format = vsp1_entity_get_pad_format(entity, config, entity->source_pad);
*format = fmt->format;
- /* Reset the crop and compose rectangles */
+ /* Reset the crop and compose rectangles. */
selection = vsp1_entity_get_pad_selection(entity, config, fmt->pad,
V4L2_SEL_TGT_CROP);
selection->left = 0;
vsp1_rpf_write(rpf, dlb, VI6_RPF_INFMT, infmt);
vsp1_rpf_write(rpf, dlb, VI6_RPF_DSWAP, fmtinfo->swap);
- /* Output location */
+ /* Output location. */
if (pipe->brx) {
const struct v4l2_rect *compose;
/*
* Interlaced pipelines will use the extended pre-cmd to process
- * SRCM_ADDR_{Y,C0,C1}
+ * SRCM_ADDR_{Y,C0,C1}.
*/
if (pipe->interlaced) {
vsp1_rpf_configure_autofld(rpf, dl);
output = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
SRU_PAD_SOURCE);
- /* Adapt if SRUx2 is enabled */
+ /* Adapt if SRUx2 is enabled. */
if (input->width != output->width) {
window->width /= 2;
window->left /= 2;
output = vsp1_entity_get_pad_format(&uds->entity, uds->entity.config,
UDS_PAD_SOURCE);
- /* Input size clipping */
+ /* Input size clipping. */
vsp1_uds_write(uds, dlb, VI6_UDS_HSZCLIP, VI6_UDS_HSZCLIP_HCEN |
(0 << VI6_UDS_HSZCLIP_HCL_OFST_SHIFT) |
(partition->uds_sink.width
<< VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT));
- /* Output size clipping */
+ /* Output size clipping. */
vsp1_uds_write(uds, dlb, VI6_UDS_CLIP_SIZE,
(partition->uds_source.width
<< VI6_UDS_CLIP_SIZE_HSIZE_SHIFT) |
const struct v4l2_mbus_framefmt *output;
const struct v4l2_mbus_framefmt *input;
- /* Initialise the partition state */
+ /* Initialise the partition state. */
partition->uds_sink = *window;
partition->uds_source = *window;
pipe->stream_config = NULL;
pipe->configured = false;
- /* Release our partition table allocation */
+ /* Release our partition table allocation. */
kfree(pipe->part_table);
pipe->part_table = NULL;
}
vsp1_wpf_write(wpf, dlb, VI6_WPF_SRCRPF, srcrpf);
- /* Enable interrupts */
+ /* Enable interrupts. */
vsp1_dl_body_write(dlb, VI6_WPF_IRQ_STA(wpf->entity.index), 0);
vsp1_dl_body_write(dlb, VI6_WPF_IRQ_ENB(wpf->entity.index),
VI6_WFP_IRQ_ENB_DFEE);