drm/amd/display: add null checks and set update flags

* add plane state null checks
* add and set update surface flags

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 700278216424ff64ddb39765022935528b226636..f469394751c10846540271fb5d9e08969ceeebe6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1358,6 +1358,9 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
        if (u->plane_info->global_alpha_value != u->surface->global_alpha_value)
                update_flags->bits.global_alpha_change = 1;
 
+       if (u->plane_info->sdr_white_level != u->surface->sdr_white_level)
+               update_flags->bits.sdr_white_level = 1;
+
        if (u->plane_info->dcc.enable != u->surface->dcc.enable
                        || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
                        || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
@@ -1461,6 +1464,9 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
 
        update_flags->raw = 0; // Reset all flags
 
+       if (u->flip_addr)
+               update_flags->bits.addr_update = 1;
+
        if (!is_surface_in_context(context, u->surface)) {
                update_flags->bits.new_plane = 1;
                return UPDATE_TYPE_FULL;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d9bfffb2c48dbbac260c9e91185392bf89ec374d..262d07a8cb75358f19545ce46fdedcfec6cbaa3d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2497,7 +2497,6 @@ void dc_resource_state_copy_construct(
 
                if (cur_pipe->bottom_pipe)
                        cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
-
        }
 
        for (i = 0; i < dst_ctx->stream_count; i++) {

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 425e2df0809f4bec1d683ade4c8e139388960ed7..7d459362601d5d427ef59bafc80e53580162209f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -541,12 +541,14 @@ struct dc_plane_status {
 union surface_update_flags {
 
        struct {
+               uint32_t addr_update:1;
                /* Medium updates */
                uint32_t dcc_change:1;
                uint32_t color_space_change:1;
                uint32_t horizontal_mirror_change:1;
                uint32_t per_pixel_alpha_change:1;
                uint32_t global_alpha_change:1;
+               uint32_t sdr_white_level:1;
                uint32_t rotation_change:1;
                uint32_t swizzle_change:1;
                uint32_t scaling_change:1;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c2b60b1e1a25d90e6d3dc35902fc299c2cb9dcc8..bf0db874d99fc815d854ba030b9eebb8d762a4a0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1755,7 +1755,7 @@ static void dcn10_program_output_csc(struct dc *dc,
 
 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
-       if (pipe_ctx->plane_state->visible)
+       if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
                return true;
        if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
                return true;
@@ -1764,7 +1764,7 @@ bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 
 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
-       if (pipe_ctx->plane_state->visible)
+       if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
                return true;
        if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
                return true;
@@ -1773,7 +1773,7 @@ bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 
 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
-       if (pipe_ctx->plane_state->visible)
+       if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
                return true;
        if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
                return true;
@@ -1919,7 +1919,7 @@ static uint16_t fixed_point_to_int_frac(
        return result;
 }
 
-void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
+void dcn10_build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
                const struct dc_plane_state *plane_state)
 {
        if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
@@ -1952,7 +1952,7 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
                        plane_state->color_space);
 
        //set scale and bias registers
-       build_prescale_params(&bns_params, plane_state);
+       dcn10_build_prescale_params(&bns_params, plane_state);
        if (dpp->funcs->dpp_program_bias_and_scale)
                dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 }
@@ -2641,9 +2641,6 @@ static void dcn10_wait_for_mpcc_disconnect(
                        res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
                        pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
                        hubp->funcs->set_blank(hubp, true);
-                       /*DC_LOG_ERROR(dc->ctx->logger,
-                                       "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
-                                       i);*/
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 4b3b27a5d23b476675bb1320fbacd8ed03187673..ef94d6b15843fa9b228318091913df0e4a51740a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -83,6 +83,8 @@ struct pipe_ctx *find_top_pipe_for_stream(
 
 int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
 
+void dcn10_build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
+               const struct dc_plane_state *plane_state);
 void lock_all_pipes(struct dc *dc,
        struct dc_state *context,
        bool lock);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 6f5ab05d64677963c984afd7a9f06943801d3e1c..d61efa068c9a0089a415925d18155086da43df88 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -212,6 +212,25 @@ struct plane_resource {
        struct dcn_fe_bandwidth bw;
 };
 
+union pipe_update_flags {
+       struct {
+               uint32_t enable : 1;
+               uint32_t disable : 1;
+               uint32_t odm : 1;
+               uint32_t global_sync : 1;
+               uint32_t opp_changed : 1;
+               uint32_t tg_changed : 1;
+               uint32_t mpcc : 1;
+               uint32_t dppclk : 1;
+               uint32_t hubp_interdependent : 1;
+               uint32_t hubp_rq_dlg_ttu : 1;
+               uint32_t gamut_remap : 1;
+               uint32_t scaler : 1;
+               uint32_t viewport : 1;
+       } bits;
+       uint32_t raw;
+};
+
 struct pipe_ctx {
        struct dc_plane_state *plane_state;
        struct dc_stream_state *stream;
@@ -234,6 +253,7 @@ struct pipe_ctx {
        struct _vcs_dpi_display_rq_regs_st rq_regs;
        struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
 #endif
+       union pipe_update_flags update_flags;
 };
 
 struct resource_context {