drm/i915/icl: Enable ICL Pipe CSC block

Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.

ToDO: Extend the ABI to accept 32 bit coefficient values
instead of 16bit for future platforms.

v2: Addressed Maarten's review comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Addressed Matt's review comments.

v5: Addressed Ville's review comments.

v6: Separated pipe output csc programming from regular csc.

v7: Rebase

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1549893025-21837-4-git-send-email-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13a207a06235fbd673cd454c7c654afe9829962f..4cb0013f43f66c6ca5bb08c540ca030695e8b396 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9885,10 +9885,13 @@ enum skl_power_gate {
 #define _PIPE_A_CSC_COEFF_BU   0x4901c
 #define _PIPE_A_CSC_COEFF_RV_GV        0x49020
 #define _PIPE_A_CSC_COEFF_BV   0x49024
+
 #define _PIPE_A_CSC_MODE       0x49028
-#define   CSC_BLACK_SCREEN_OFFSET      (1 << 2)
-#define   CSC_POSITION_BEFORE_GAMMA    (1 << 1)
-#define   CSC_MODE_YUV_TO_RGB          (1 << 0)
+#define  ICL_CSC_ENABLE                        (1 << 31)
+#define  CSC_BLACK_SCREEN_OFFSET       (1 << 2)
+#define  CSC_POSITION_BEFORE_GAMMA     (1 << 1)
+#define  CSC_MODE_YUV_TO_RGB           (1 << 0)
+
 #define _PIPE_A_CSC_PREOFF_HI  0x49030
 #define _PIPE_A_CSC_PREOFF_ME  0x49034
 #define _PIPE_A_CSC_PREOFF_LO  0x49038

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index c5bd0f97e9a87356c6d7a9dfb50ddeaf65f43eaf..395b475c57ce8d4a448a99d917510f160ae582f6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -243,7 +243,10 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
                I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
                I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-               I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+               if (INTEL_GEN(dev_priv) >= 11)
+                       I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
+               else
+                       I915_WRITE(PIPE_CSC_MODE(pipe), 0);
        } else {
                u32 mode = CSC_MODE_YUV_TO_RGB;