ARM: tegra: set up wlan clocks for tegra dt

Set up the wlan clock tree for Tegra20 and Tegra30.

Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 71569c01afd26311aa7b1cf163fcc259700c9f3e..0419056e53bd4e4e621c39a8aeeea4e81d94fc6a 100644 (file)
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -102,8 +102,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
        { "pll_a",      "pll_p_out1",   56448000,       true },
        { "pll_a_out0", "pll_a",        11289600,       true },
        { "cdev1",      NULL,           0,              true },
+       { "blink",      "clk_32k",      32768,          true },
        { "i2s1",       "pll_a_out0",   11289600,       false},
        { "i2s2",       "pll_a_out0",   11289600,       false},
+       { "sdmmc1",     "pll_p",        48000000,       false},
+       { "sdmmc3",     "pll_p",        48000000,       false},
+       { "sdmmc4",     "pll_p",        48000000,       false},
        { NULL,         NULL,           0,              0},
 };
 

diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index e56170393a5bd265d16b99c32791bc03b5200484..7368ebdbafc502709ba1ded5690d186cc69d5980 100644 (file)
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -61,11 +61,15 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
        { "pll_a_out0", "pll_a",        11289600,       true },
        { "extern1",    "pll_a_out0",   0,              true },
        { "clk_out_1",  "extern1",      0,              true },
+       { "blink",      "clk_32k",      32768,          true },
        { "i2s0",       "pll_a_out0",   11289600,       false},
        { "i2s1",       "pll_a_out0",   11289600,       false},
        { "i2s2",       "pll_a_out0",   11289600,       false},
        { "i2s3",       "pll_a_out0",   11289600,       false},
        { "i2s4",       "pll_a_out0",   11289600,       false},
+       { "sdmmc1",     "pll_p",        48000000,       false},
+       { "sdmmc3",     "pll_p",        48000000,       false},
+       { "sdmmc4",     "pll_p",        48000000,       false},
        { NULL,         NULL,           0,              0},
 };