drm/i915: Fix HSW power well control state read

Fix power well control state by reading real register offset.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f85043ca41b5705f632c192bf57807ae69b6a2be..59c31f6238c19985ed530c23d7098f5365005102 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3842,7 +3842,7 @@ void intel_init_power_wells(struct drm_device *dev)
 
                if ((well & HSW_PWR_WELL_STATE) == 0) {
                        I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
-                       if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
+                       if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
                                DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
                }
        }