drm/i915: Set guardband clipping workaround bit in the right register.

A previous patch, namely:

commit bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Apr 11 20:42:41 2012 +0200

    drm/i915: implement w/a for incorrect guarband clipping

accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with
clipping.  This patch changes it to be set in 3D_CHICKEN3, where it
belongs.

The game "Dante" demonstrates random clipping issues when guardband
clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set.  So the
workaround is actually necessary.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64c1be0a9cfdb033ab33e66da2463b8b28fc8ffb..a4162ddff6c5e0e38c3c7b298aa4806d02bcb992 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,7 +521,7 @@
  */
 # define _3D_CHICKEN2_WM_READ_PIPELINED                        (1 << 14)
 #define _3D_CHICKEN3   0x02090
-#define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL          (1 << 5)
+#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL         (1 << 5)
 
 #define MI_MODE                0x0209c
 # define VS_TIMER_DISPATCH                             (1 << 6)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b3b4b6cea8b001e4c31e79604fe56015a1bcae11..72f41aaa71ff330637bdc82d4ee8e0c04091bdf2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3442,8 +3442,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
        /* Bspec says we need to always set all mask bits. */
-       I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
-                  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
+       I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
+                  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
 
        /*
         * According to the spec the following bits should be