mmc: sunxi: Keep default timing phase settings for new timing mode

The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whole register.

Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
controllers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d6fa2214aaae8f967bf34230f7d784b4c598718b..0fb4e4c119e10682b2a2860f5389cd6350bcbb82 100644 (file)
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
        }
        mmc_writel(host, REG_CLKCR, rval);
 
-       if (host->cfg->needs_new_timings)
-               mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
+       if (host->cfg->needs_new_timings) {
+               /* Don't touch the delay bits */
+               rval = mmc_readl(host, REG_SD_NTSR);
+               rval |= SDXC_2X_TIMING_MODE;
+               mmc_writel(host, REG_SD_NTSR, rval);
+       }
 
        ret = sunxi_mmc_clk_set_phase(host, ios, rate);
        if (ret)