ARM: at91: pm: do not disable/enable PLLA for ULP modes

There is no need to disable/enable PLLA when switching to one of the
ULP modes. The PLLA consumers should take care of this.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 5c33023f9129ecaa36669dfd12e9b3b8979be1d8..77e29309cc6e918fbc2f288e776b80ba6816e528 100644 (file)
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -50,15 +50,6 @@ tmp2 .req    r5
        beq     1b
        .endm
 
-/*
- * Wait until PLLA has locked.
- */
-       .macro wait_pllalock
-1:     ldr     tmp1, [pmc, #AT91_PMC_SR]
-       tst     tmp1, #AT91_PMC_LOCKA
-       beq     1b
-       .endm
-
 /*
  * Put the processor to enter the idle state
  */
@@ -351,14 +342,6 @@ ENTRY(at91_ulp_mode)
 
        wait_mckrdy
 
-       /* Save PLLA setting and disable it */
-       ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
-       str     tmp1, .saved_pllar
-
-       mov     tmp1, #AT91_PMC_PLLCOUNT
-       orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
-       str     tmp1, [pmc, #AT91_CKGR_PLLAR]
-
        ldr     r0, .pm_mode
        cmp     r0, #AT91_PM_ULP1
        beq     ulp1_mode
@@ -373,18 +356,6 @@ ulp1_mode:
 ulp_exit:
        ldr     pmc, .pmc_base
 
-       /* Restore PLLA setting */
-       ldr     tmp1, .saved_pllar
-       str     tmp1, [pmc, #AT91_CKGR_PLLAR]
-
-       tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
-       bne     3f
-       tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
-       beq     4f
-3:
-       wait_pllalock
-4:
-
        /*
         * Restore master clock setting
         */
@@ -537,8 +508,6 @@ ENDPROC(at91_sramc_self_refresh)
        .word 0
 .saved_mckr:
        .word 0
-.saved_pllar:
-       .word 0
 .saved_sam9_lpr:
        .word 0
 .saved_sam9_lpr1: