drm/i915: Add some missing curly braces
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 18 Mar 2019 20:26:51 +0000 (22:26 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 19 Mar 2019 14:36:38 +0000 (16:36 +0200)
Sprinkle some curly braces in accordance with the coding style.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190318202653.15217-1-ville.syrjala@linux.intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/intel_display.c

index 25fbfaabb50e092448c51692224552a6e5906702..11e6026782dc6eb037eec53a805752dc9197bcfc 100644 (file)
@@ -1622,14 +1622,15 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
        }
 
        val &= ~TRANS_INTERLACE_MASK;
-       if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+       if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
                if (HAS_PCH_IBX(dev_priv) &&
                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
                        val |= TRANS_LEGACY_INTERLACED_ILK;
                else
                        val |= TRANS_INTERLACED;
-       else
+       } else {
                val |= TRANS_PROGRESSIVE;
+       }
 
        I915_WRITE(reg, val | TRANS_ENABLE);
        if (intel_wait_for_register(dev_priv,
@@ -7760,8 +7761,9 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
                        pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                else
                        pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
-       } else
+       } else {
                pipeconf |= PIPECONF_PROGRESSIVE;
+       }
 
        if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
             crtc_state->limited_color_range)
@@ -8877,8 +8879,9 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
                     dev_priv->vbt.lvds_ssc_freq == 100000) ||
                    (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
                        factor = 25;
-       } else if (crtc_state->sdvo_tv_clock)
+       } else if (crtc_state->sdvo_tv_clock) {
                factor = 20;
+       }
 
        fp = i9xx_dpll_compute_fp(&crtc_state->dpll);