drm/nouveau/fifo/gk104-: identify mmu engine ids for host faults
authorBen Skeggs <bskeggs@redhat.com>
Fri, 8 Apr 2016 07:24:40 +0000 (17:24 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 20 May 2016 04:43:04 +0000 (14:43 +1000)
It appears these don't map to PBDMAs (at least on Kepler, it may or may
be valid for Fermi - this hasn't been checked), but to runlists.

This drops the NVKM_ENGINE_FIFO data from the entries too, as resetting
all of PFIFO is *not* the way to handle such faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

index 6e842768f5587d02b405200515cf985688be2d36..743f3a189f285dd6234a54efe6e5d50009fbf25e 100644 (file)
@@ -738,12 +738,21 @@ gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device,
 const struct nvkm_enum
 gk104_fifo_fault_engine[] = {
        { 0x00, "GR", NULL, NVKM_ENGINE_GR },
+       { 0x01, "DISPLAY" },
+       { 0x02, "CAPTURE" },
        { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
        { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
-       { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
-       { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO },
-       { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO },
-       { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO },
+       { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
+       { 0x06, "SCHED" },
+       { 0x07, "HOST0" },
+       { 0x08, "HOST1" },
+       { 0x09, "HOST2" },
+       { 0x0a, "HOST3" },
+       { 0x0b, "HOST4" },
+       { 0x0c, "HOST5" },
+       { 0x0d, "HOST6" },
+       { 0x0e, "HOST7" },
+       { 0x0f, "HOSTSR" },
        { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
        { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
        { 0x13, "PERF" },
@@ -751,6 +760,7 @@ gk104_fifo_fault_engine[] = {
        { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
        { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
        { 0x17, "PMU" },
+       { 0x18, "PTP" },
        { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
        { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
        {}