media: adv*/tc358743/ths8200: fill in min width/height/pixelclock
authorHans Verkuil <hverkuil-cisco@xs4all.nl>
Thu, 8 Nov 2018 09:51:51 +0000 (04:51 -0500)
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Fri, 23 Nov 2018 11:20:55 +0000 (06:20 -0500)
The v4l2_dv_timings_cap struct is used to do sanity checks when setting and
enumerating DV timings, ensuring that only valid timings as per the HW
capabilities are allowed.

However, many drivers just filled in 0 for the minimum width, height or
pixelclock frequency. This can cause timings with e.g. 0 as width and height
to be accepted, which will in turn lead to a potential division by zero.

Fill in proper values are minimum boundaries. 640x350 was chosen since it is
the smallest resolution in v4l2-dv-timings.h. Same for 13 MHz as the lowest
pixelclock frequency (it's slightly below the minimum of 13.5 MHz in the
v4l2-dv-timings.h header).

Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
drivers/media/i2c/ad9389b.c
drivers/media/i2c/adv7511.c
drivers/media/i2c/adv7604.c
drivers/media/i2c/adv7842.c
drivers/media/i2c/tc358743.c
drivers/media/i2c/ths8200.c

index 5b008b0002c02c185bad782c2e3fe4f8e26a23b5..aa8b04cfed0f6c3c298bba33f48345710b0d8fe5 100644 (file)
@@ -578,7 +578,7 @@ static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
                V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
index f3899cc84e27f8db4c89c63e8ab1f2593dd8432a..88349b5053cce0298734ace8ae247171cd439712 100644 (file)
@@ -130,7 +130,7 @@ static const struct v4l2_dv_timings_cap adv7511_timings_cap = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, ADV7511_MAX_WIDTH, 0, ADV7511_MAX_HEIGHT,
+       V4L2_INIT_BT_TIMINGS(640, ADV7511_MAX_WIDTH, 350, ADV7511_MAX_HEIGHT,
                ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK,
                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
index 88786276dbe4d6111668c33b4aee3fb3c9c93552..43d27edac6367ff1a8201c693031ff6affabc8c6 100644 (file)
@@ -771,7 +771,7 @@ static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
                V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
@@ -782,7 +782,7 @@ static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
                V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
index 4721d49dcf0fef4bc4048e73d49bac558e3ed13e..5305c3ad80e640c24e56f200837e24ccbd3a0da1 100644 (file)
@@ -663,7 +663,7 @@ static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
                V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
@@ -674,7 +674,7 @@ static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
                V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
index 41d470d9ca943ea84653f9dd8bfb0ab83dafe1a4..00dc930e049f90bb1e82322f8f81313c64cc9f15 100644 (file)
@@ -59,7 +59,7 @@ static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
        /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
-       V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
                        V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
                        V4L2_DV_BT_CAP_PROGRESSIVE |
index 498ad2368cbcfa56d0d84ecf26cf62e1f74375b5..f5ee28058ea2af35ae7dd137ab4f27ea3115529e 100644 (file)
@@ -49,7 +49,7 @@ static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
        .type = V4L2_DV_BT_656_1120,
        /* keep this initialization for compatibility with GCC < 4.4.6 */
        .reserved = { 0 },
-       V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1080, 25000000, 148500000,
+       V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1080, 25000000, 148500000,
                V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE)
 };