drm/amdgpu/gfx9: properly set the hdp flush reg for Raven

Was only being assigned for vega10.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2ab049c45b1d830d425981dc6f6e0f26bcdb69eb..72dbf890c65b6d022972b9abd78ec67e3263d4db 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3504,7 +3504,9 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
        u32 ref_and_mask, reg_mem_engine;
        struct nbio_hdp_flush_reg *nbio_hf_reg;
 
-       if (ring->adev->asic_type == CHIP_VEGA10)
+       if (ring->adev->flags & AMD_IS_APU)
+               nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
+       else
                nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
 
        if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {