.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
.multipoint = true,
.dyn_fifo = true,
- .soft_con = true,
.num_eps = SUNXI_MUSB_MAX_EP_NUM,
.ram_bits = SUNXI_MUSB_RAM_BITS,
- .dma = 0,
};
static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = {
.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
.multipoint = true,
.dyn_fifo = true,
- .soft_con = true,
.num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
.ram_bits = SUNXI_MUSB_RAM_BITS,
- .dma = 0,
};
/* MUSB configuration-specific details */
unsigned multipoint:1; /* multipoint device */
unsigned dyn_fifo:1 __deprecated; /* supports dynamic fifo sizing */
- unsigned soft_con:1 __deprecated; /* soft connect required */
- unsigned utm_16:1 __deprecated; /* utm data witdh is 16 bits */
- unsigned big_endian:1; /* true if CPU uses big-endian */
- unsigned mult_bulk_tx:1; /* Tx ep required for multbulk pkts */
- unsigned mult_bulk_rx:1; /* Rx ep required for multbulk pkts */
- unsigned high_iso_tx:1; /* Tx ep required for HB iso */
- unsigned high_iso_rx:1; /* Rx ep required for HD iso */
- unsigned dma:1 __deprecated; /* supports DMA */
- unsigned vendor_req:1 __deprecated; /* vendor registers required */
/* need to explicitly de-assert the port reset after resume? */
unsigned host_port_deassert_reset_at_resume:1;
u8 num_eps; /* number of endpoints _with_ ep0 */
- u8 dma_channels __deprecated; /* number of dma channels */
- u8 dyn_fifo_size; /* dynamic size in bytes */
- u8 vendor_ctrl __deprecated; /* vendor control reg width */
- u8 vendor_stat __deprecated; /* vendor status reg witdh */
- u8 dma_req_chan __deprecated; /* bitmask for required dma channels */
u8 ram_bits; /* ram address size */
- struct musb_hdrc_eps_bits *eps_bits __deprecated;
u32 maximum_speed;
};