return patch_size;
}
+/*
+ * Check the current patch level on this CPU.
+ *
+ * @rev: Use it to return the patch level. It is set to 0 in the case of
+ * error.
+ *
+ * Returns:
+ * - true: if update should stop
+ * - false: otherwise
+ */
+bool check_current_patch_level(u32 *rev)
+{
+ u32 dummy;
+
+ native_rdmsr(MSR_AMD64_PATCH_LEVEL, *rev, dummy);
+
+ return false;
+}
+
int __apply_microcode_amd(struct microcode_amd *mc_amd)
{
u32 rev, dummy;
struct microcode_amd *mc_amd;
struct ucode_cpu_info *uci;
struct ucode_patch *p;
- u32 rev, dummy;
+ u32 rev;
BUG_ON(raw_smp_processor_id() != cpu);
mc_amd = p->data;
uci->mc = p->data;
- rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
+ if (check_current_patch_level(&rev))
+ return -1;
/* need to apply patch? */
if (rev >= mc_amd->hdr.patch_id) {
return;
}
- /* find ucode and update if needed */
-
- native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
+ if (check_current_patch_level(&rev))
+ return;
while (left > 0) {
struct microcode_amd *mc;
void load_ucode_amd_ap(void)
{
unsigned int cpu = smp_processor_id();
- struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
struct equiv_cpu_entry *eq;
struct microcode_amd *mc;
u32 rev, eax;
if (!container)
return;
- rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
-
- uci->cpu_sig.rev = rev;
- uci->cpu_sig.sig = eax;
+ if (check_current_patch_level(&rev))
+ return;
eax = cpuid_eax(0x00000001);
eq = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
void reload_ucode_amd(void)
{
struct microcode_amd *mc;
- u32 rev, eax;
+ u32 rev;
- rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
+ if (check_current_patch_level(&rev))
+ return;
mc = (struct microcode_amd *)amd_ucode_patch;