drm/i915/icl: split combo and tbt pll funcs

Like was done for MG and combo, now finish the per-type split of the
vfunc by moving TBT out of the combo functions. Now we can completely
remove icl_pll_id_to_enable_reg() since each PLL type passes all the
information via arguments.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-5-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index f13ec0ba1d8498c4424c3d49d7c640c32bf59727..97056b8ac869136681175ada4359c08bbb490bbd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2956,16 +2956,6 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
        return pll;
 }
 
-static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
-{
-       if (intel_dpll_is_combophy(id))
-               return CNL_DPLL_ENABLE(id);
-       else if (id == DPLL_ID_ICL_TBTPLL)
-               return TBT_PLL_ENABLE;
-
-       return MG_PLL_ENABLE(icl_pll_id_to_tc_port(id));
-}
-
 static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
                                struct intel_shared_dpll *pll,
                                struct intel_dpll_hw_state *hw_state)
@@ -3030,7 +3020,8 @@ out:
 
 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
                                 struct intel_shared_dpll *pll,
-                                struct intel_dpll_hw_state *hw_state)
+                                struct intel_dpll_hw_state *hw_state,
+                                i915_reg_t enable_reg)
 {
        const enum intel_dpll_id id = pll->info->id;
        intel_wakeref_t wakeref;
@@ -3042,7 +3033,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
        if (!wakeref)
                return false;
 
-       val = I915_READ(icl_pll_id_to_enable_reg(id));
+       val = I915_READ(enable_reg);
        if (!(val & PLL_ENABLE))
                goto out;
 
@@ -3055,6 +3046,21 @@ out:
        return ret;
 }
 
+static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
+                                  struct intel_shared_dpll *pll,
+                                  struct intel_dpll_hw_state *hw_state)
+{
+       return icl_pll_get_hw_state(dev_priv, pll, hw_state,
+                                   CNL_DPLL_ENABLE(pll->info->id));
+}
+
+static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
+                                struct intel_shared_dpll *pll,
+                                struct intel_dpll_hw_state *hw_state)
+{
+       return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE);
+}
+
 static void icl_dpll_write(struct drm_i915_private *dev_priv,
                           struct intel_shared_dpll *pll)
 {
@@ -3154,7 +3160,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
                             struct intel_shared_dpll *pll)
 {
-       i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+       i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
 
        icl_pll_power_enable(dev_priv, pll, enable_reg);
 
@@ -3171,6 +3177,24 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
        /* DVFS post sequence would be here. See the comment above. */
 }
 
+static void tbt_pll_enable(struct drm_i915_private *dev_priv,
+                          struct intel_shared_dpll *pll)
+{
+       icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE);
+
+       icl_dpll_write(dev_priv, pll);
+
+       /*
+        * DVFS pre sequence would be here, but in our driver the cdclk code
+        * paths should already be setting the appropriate voltage, hence we do
+        * nothing here.
+        */
+
+       icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE);
+
+       /* DVFS post sequence would be here. See the comment above. */
+}
+
 static void mg_pll_enable(struct drm_i915_private *dev_priv,
                          struct intel_shared_dpll *pll)
 {
@@ -3232,9 +3256,13 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
                              struct intel_shared_dpll *pll)
 {
-       i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+       icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
+}
 
-       icl_pll_disable(dev_priv, pll, enable_reg);
+static void tbt_pll_disable(struct drm_i915_private *dev_priv,
+                           struct intel_shared_dpll *pll)
+{
+       icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE);
 }
 
 static void mg_pll_disable(struct drm_i915_private *dev_priv,
@@ -3268,10 +3296,16 @@ static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
                      hw_state->mg_pll_tdc_coldst_bias);
 }
 
-static const struct intel_shared_dpll_funcs icl_pll_funcs = {
+static const struct intel_shared_dpll_funcs combo_pll_funcs = {
        .enable = combo_pll_enable,
        .disable = combo_pll_disable,
-       .get_hw_state = icl_pll_get_hw_state,
+       .get_hw_state = combo_pll_get_hw_state,
+};
+
+static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
+       .enable = tbt_pll_enable,
+       .disable = tbt_pll_disable,
+       .get_hw_state = tbt_pll_get_hw_state,
 };
 
 static const struct intel_shared_dpll_funcs mg_pll_funcs = {
@@ -3281,9 +3315,9 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
 };
 
 static const struct dpll_info icl_plls[] = {
-       { "DPLL 0",   &icl_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
-       { "DPLL 1",   &icl_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
-       { "TBT PLL",  &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+       { "DPLL 0",   &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
+       { "DPLL 1",   &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
+       { "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
        { "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
        { "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
        { "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },