ARM: mediatek: dts: Add uart to mt6589

This patch adds the uart ports to the device tree of Mediatek mt6589 SoC.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index c91b2a9ebdc323c1d8f8e2c94a371c6421cd7eef..106b61b1003032e88ca8a679ed1d2d56da561f10 100644 (file)
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -65,6 +65,12 @@
                        clock-frequency = <32000>;
                        #clock-cells = <0>;
                };
+
+               uart_clk: dummy26m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <26000000>;
+                       #clock-cells = <0>;
+               };
        };
 
        soc {
@@ -100,5 +106,37 @@
                              <0x10214000 0x2000>,
                              <0x10216000 0x2000>;
                };
+
+               uart0: serial@11006000 {
+                       compatible = "mediatek,mt6577-uart";
+                       reg = <0x11006000 0x400>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart1: serial@11007000 {
+                       compatible = "mediatek,mt6577-uart";
+                       reg = <0x11007000 0x400>;
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@11008000 {
+                       compatible = "mediatek,mt6577-uart";
+                       reg = <0x11008000 0x400>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart3: serial@11009000 {
+                       compatible = "mediatek,mt6577-uart";
+                       reg = <0x11009000 0x400>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
        };
 };