x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk

The MC4_MISC thresholding quirk needs to be applied during S5 -> S0 and
S3 -> S0 state transitions, which follow different code paths. Carve it
out into a separate function and call it mce_amd_feature_init() where
the two code paths of the state transitions converge.

 [ bp: massage commit message and the carved out function. ]

Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1547651417-23583-3-git-send-email-shirish.s@amd.com

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 89298c83de53b226227d4271ee5fcc85f2a118fc..ed3327342b40ef6eee6a866cf42dafbb03608d88 100644 (file)
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -545,6 +545,40 @@ out:
        return offset;
 }
 
+/*
+ * Turn off MC4_MISC thresholding banks on all family 0x15 models since
+ * they're not supported there.
+ */
+void disable_err_thresholding(struct cpuinfo_x86 *c)
+{
+       int i;
+       u64 hwcr;
+       bool need_toggle;
+       u32 msrs[] = {
+               0x00000413, /* MC4_MISC0 */
+               0xc0000408, /* MC4_MISC1 */
+       };
+
+       if (c->x86 != 0x15)
+               return;
+
+       rdmsrl(MSR_K7_HWCR, hwcr);
+
+       /* McStatusWrEn has to be set */
+       need_toggle = !(hwcr & BIT(18));
+
+       if (need_toggle)
+               wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
+
+       /* Clear CntP bit safely */
+       for (i = 0; i < ARRAY_SIZE(msrs); i++)
+               msr_clear_bit(msrs[i], 62);
+
+       /* restore old settings */
+       if (need_toggle)
+               wrmsrl(MSR_K7_HWCR, hwcr);
+}
+
 /* cpu init entry point, called from mce.c with preempt off */
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
@@ -552,6 +586,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
        unsigned int bank, block, cpu = smp_processor_id();
        int offset = -1;
 
+       disable_err_thresholding(c);
+
        for (bank = 0; bank < mca_cfg.banks; ++bank) {
                if (mce_flags.smca)
                        smca_configure(bank, cpu);

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index d0c54160b43903d14c511be62faf6facd9f90a76..6063ae2376b2d61742f9c2225246f3f678c95dec 100644 (file)
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1611,35 +1611,6 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
                if (c->x86 == 0x15 && c->x86_model <= 0xf)
                        mce_flags.overflow_recov = 1;
 
-               /*
-                * Turn off MC4_MISC thresholding banks on all models since
-                * they're not supported there.
-                */
-               if (c->x86 == 0x15) {
-                       int i;
-                       u64 hwcr;
-                       bool need_toggle;
-                       u32 msrs[] = {
-                               0x00000413, /* MC4_MISC0 */
-                               0xc0000408, /* MC4_MISC1 */
-                       };
-
-                       rdmsrl(MSR_K7_HWCR, hwcr);
-
-                       /* McStatusWrEn has to be set */
-                       need_toggle = !(hwcr & BIT(18));
-
-                       if (need_toggle)
-                               wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
-
-                       /* Clear CntP bit safely */
-                       for (i = 0; i < ARRAY_SIZE(msrs); i++)
-                               msr_clear_bit(msrs[i], 62);
-
-                       /* restore old settings */
-                       if (need_toggle)
-                               wrmsrl(MSR_K7_HWCR, hwcr);
-               }
        }
 
        if (c->x86_vendor == X86_VENDOR_INTEL) {