ramips: mt7620: ethernet: use more macros and bump version

Define and use some missing macros,
and use them instead of BIT() or numbers for more readable code.

Add comment for a bit change that seems unrelated to ethernet
but is actually needed (PCIe Root Complex mode).

Remove unknown and unused macro RST_CTRL_MCM
(probably from MT7621 / MT7622)

This is the last of a series of fixes, so bump version.

Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 88a0cebadfecb6ebb9f5f535e74f7f7574f513f3)

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
index ae90f0484daeec2761418799527e0b8055a5eb4a..7c91e5840b64f0667cc343b908f40dea6787cdc6 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
@@ -65,9 +65,11 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw)
 {
        u32 i;
        u32 val;
-       u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
+       u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
+
+       /* Internal ethernet requires PCIe RC mode */
+       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
 
-       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
        mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 
        /* Enable MIB stats */
@@ -83,7 +85,7 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw)
                mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
                        (gsw->ephy_base << 16),
                        GSW_REG_GPC1);
-               fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
+               fe_reset(MT7620A_RESET_EPHY);
 
                pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
        }

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h
index fde7792c023b820ead453fd1ddeb50f7fbc820a7..cb5d098e9cea48cc085c400834b1570026c00d8c 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h
@@ -55,7 +55,7 @@
 
 #define SYSC_REG_CHIP_REV_ID   0x0c
 #define SYSC_REG_CFG1          0x14
-#define RST_CTRL_MCM           BIT(2)
+#define PCIE_RC_MODE           BIT(8)
 #define SYSC_PAD_RGMII2_MDIO   0x58
 #define SYSC_GPIO_MODE         0x60
 

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
index 00f1a0e7e6a4ddda1165f25289acb5e6fd97e91f..c8517f9f9d101acba3aec12bec97ed7181ed2465 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
@@ -49,7 +49,7 @@ enum fe_work_flag {
        FE_FLAG_MAX
 };
 
-#define MTK_FE_DRV_VERSION             "0.1.2"
+#define MTK_FE_DRV_VERSION             "0.2"
 
 /* power of 2 to let NEXT_TX_DESP_IDX work */
 #define NUM_DMA_DESC           BIT(10)
@@ -157,6 +157,10 @@ enum fe_work_flag {
 #define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
 #define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
 
+#define MT7620A_RESET_FE       BIT(21)
+#define MT7620A_RESET_ESW      BIT(23)
+#define MT7620A_RESET_EPHY     BIT(24)
+
 #define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
 #define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
 #define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index c596de76bd2a08cceade05f311e057a81218893a..2470e7a3c1cbb36d30764052ed623b087796fa15 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -27,8 +27,6 @@
 
 #define MT7620A_CDMA_CSG_CFG   0x400
 #define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
-#define MT7620A_RESET_FE       BIT(21)
-#define MT7620A_RESET_ESW      BIT(23)
 #define MT7620_L4_VALID                BIT(23)
 
 #define MT7620_TX_DMA_UDF      BIT(15)