int rval;
uint32_t cnt, timer;
uint32_t risc_address;
- uint16_t mb[4];
+ uint16_t mb[4], wd;
uint32_t stat;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
WRT_REG_DWORD(®->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
- RD_REG_DWORD(®->ctrl_status);
+ pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
+ udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
- udelay(5);
mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0);
for (cnt = 10000 ; cnt && mb[0]; cnt--) {
udelay(5);
barrier();
}
- udelay(20);
+ /* Wait for soft-reset to complete. */
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_DWORD(®->ctrl_status) &
CSRX_ISP_SOFT_RESET) == 0)
unsigned long flags = 0;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
uint32_t cnt, d2;
+ uint16_t wd;
spin_lock_irqsave(&ha->hardware_lock, flags);
WRT_REG_DWORD(®->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
- RD_REG_DWORD(®->ctrl_status);
+ pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
+ udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
- udelay(5);
d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
for (cnt = 10000 ; cnt && d2; cnt--) {
udelay(5);
barrier();
}
- udelay(20);
+ /* Wait for soft-reset to complete. */
d2 = RD_REG_DWORD(®->ctrl_status);
for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
udelay(5);