drm/amd/display: fix dcn1 watermark range reporting

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index ac4451adeec9f25c04c4dab8d018d0f17467c547..8dc0773b285ebdc94865c8e6bd9489cf20ecbb94 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1335,21 +1335,14 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 {
        struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
        struct pp_smu_wm_range_sets ranges = {0};
-       int max_fclk_khz, nom_fclk_khz, mid_fclk_khz, min_fclk_khz;
-       int max_dcfclk_khz, min_dcfclk_khz;
-       int socclk_khz;
+       int min_fclk_khz, min_dcfclk_khz, socclk_khz;
        const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
-       unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
 
        if (!pp->set_wm_ranges)
                return;
 
        kernel_fpu_begin();
-       max_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
-       nom_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
-       mid_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor;
        min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
-       max_dcfclk_khz = dc->dcn_soc->dcfclkv_max0p9 * 1000;
        min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
        socclk_khz = dc->dcn_soc->socclk * 1000;
        kernel_fpu_end();
@@ -1357,7 +1350,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
        /* Now notify PPLib/SMU about which Watermarks sets they should select
         * depending on DPM state they are in. And update BW MGR GFX Engine and
         * Memory clock member variables for Watermarks calculations for each
-        * Watermark Set
+        * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
         */
        /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
         * care what the value is, hence min to overdrive level
@@ -1366,96 +1359,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
        ranges.num_writer_wm_sets = WM_SET_COUNT;
        ranges.reader_wm_sets[0].wm_inst = WM_A;
        ranges.reader_wm_sets[0].min_drain_clk_khz = min_dcfclk_khz;
-       ranges.reader_wm_sets[0].max_drain_clk_khz = max_dcfclk_khz;
+       ranges.reader_wm_sets[0].max_drain_clk_khz = overdrive;
        ranges.reader_wm_sets[0].min_fill_clk_khz = min_fclk_khz;
-       ranges.reader_wm_sets[0].max_fill_clk_khz = min_fclk_khz;
+       ranges.reader_wm_sets[0].max_fill_clk_khz = overdrive;
        ranges.writer_wm_sets[0].wm_inst = WM_A;
        ranges.writer_wm_sets[0].min_fill_clk_khz = socclk_khz;
        ranges.writer_wm_sets[0].max_fill_clk_khz = overdrive;
        ranges.writer_wm_sets[0].min_drain_clk_khz = min_fclk_khz;
-       ranges.writer_wm_sets[0].max_drain_clk_khz = min_fclk_khz;
-
-       ranges.reader_wm_sets[1].wm_inst = WM_B;
-       ranges.reader_wm_sets[1].min_drain_clk_khz = min_fclk_khz;
-       ranges.reader_wm_sets[1].max_drain_clk_khz = max_dcfclk_khz;
-       ranges.reader_wm_sets[1].min_fill_clk_khz = mid_fclk_khz;
-       ranges.reader_wm_sets[1].max_fill_clk_khz = mid_fclk_khz;
-       ranges.writer_wm_sets[1].wm_inst = WM_B;
-       ranges.writer_wm_sets[1].min_fill_clk_khz = socclk_khz;
-       ranges.writer_wm_sets[1].max_fill_clk_khz = overdrive;
-       ranges.writer_wm_sets[1].min_drain_clk_khz = mid_fclk_khz;
-       ranges.writer_wm_sets[1].max_drain_clk_khz = mid_fclk_khz;
-
-
-       ranges.reader_wm_sets[2].wm_inst = WM_C;
-       ranges.reader_wm_sets[2].min_drain_clk_khz = min_fclk_khz;
-       ranges.reader_wm_sets[2].max_drain_clk_khz = max_dcfclk_khz;
-       ranges.reader_wm_sets[2].min_fill_clk_khz = nom_fclk_khz;
-       ranges.reader_wm_sets[2].max_fill_clk_khz = nom_fclk_khz;
-       ranges.writer_wm_sets[2].wm_inst = WM_C;
-       ranges.writer_wm_sets[2].min_fill_clk_khz = socclk_khz;
-       ranges.writer_wm_sets[2].max_fill_clk_khz = overdrive;
-       ranges.writer_wm_sets[2].min_drain_clk_khz = nom_fclk_khz;
-       ranges.writer_wm_sets[2].max_drain_clk_khz = nom_fclk_khz;
-
-       ranges.reader_wm_sets[3].wm_inst = WM_D;
-       ranges.reader_wm_sets[3].min_drain_clk_khz = min_fclk_khz;
-       ranges.reader_wm_sets[3].max_drain_clk_khz = max_dcfclk_khz;
-       ranges.reader_wm_sets[3].min_fill_clk_khz = max_fclk_khz;
-       ranges.reader_wm_sets[3].max_fill_clk_khz = max_fclk_khz;
-       ranges.writer_wm_sets[3].wm_inst = WM_D;
-       ranges.writer_wm_sets[3].min_fill_clk_khz = socclk_khz;
-       ranges.writer_wm_sets[3].max_fill_clk_khz = overdrive;
-       ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz;
-       ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz;
+       ranges.writer_wm_sets[0].max_drain_clk_khz = overdrive;
 
        if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
                ranges.reader_wm_sets[0].wm_inst = WM_A;
                ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;
-               ranges.reader_wm_sets[0].max_drain_clk_khz = 654000;
+               ranges.reader_wm_sets[0].max_drain_clk_khz = 5000000;
                ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;
-               ranges.reader_wm_sets[0].max_fill_clk_khz = 800000;
+               ranges.reader_wm_sets[0].max_fill_clk_khz = 5000000;
                ranges.writer_wm_sets[0].wm_inst = WM_A;
                ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;
-               ranges.writer_wm_sets[0].max_fill_clk_khz = 757000;
+               ranges.writer_wm_sets[0].max_fill_clk_khz = 5000000;
                ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;
-               ranges.writer_wm_sets[0].max_drain_clk_khz = 800000;
-
-               ranges.reader_wm_sets[1].wm_inst = WM_B;
-               ranges.reader_wm_sets[1].min_drain_clk_khz = 300000;
-               ranges.reader_wm_sets[1].max_drain_clk_khz = 654000;
-               ranges.reader_wm_sets[1].min_fill_clk_khz = 933000;
-               ranges.reader_wm_sets[1].max_fill_clk_khz = 933000;
-               ranges.writer_wm_sets[1].wm_inst = WM_B;
-               ranges.writer_wm_sets[1].min_fill_clk_khz = 200000;
-               ranges.writer_wm_sets[1].max_fill_clk_khz = 757000;
-               ranges.writer_wm_sets[1].min_drain_clk_khz = 933000;
-               ranges.writer_wm_sets[1].max_drain_clk_khz = 933000;
-
-
-               ranges.reader_wm_sets[2].wm_inst = WM_C;
-               ranges.reader_wm_sets[2].min_drain_clk_khz = 300000;
-               ranges.reader_wm_sets[2].max_drain_clk_khz = 654000;
-               ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000;
-               ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000;
-               ranges.writer_wm_sets[2].wm_inst = WM_C;
-               ranges.writer_wm_sets[2].min_fill_clk_khz = 200000;
-               ranges.writer_wm_sets[2].max_fill_clk_khz = 757000;
-               ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000;
-               ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000;
-
-               ranges.reader_wm_sets[3].wm_inst = WM_D;
-               ranges.reader_wm_sets[3].min_drain_clk_khz = 300000;
-               ranges.reader_wm_sets[3].max_drain_clk_khz = 654000;
-               ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000;
-               ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000;
-               ranges.writer_wm_sets[3].wm_inst = WM_D;
-               ranges.writer_wm_sets[3].min_fill_clk_khz = 200000;
-               ranges.writer_wm_sets[3].max_fill_clk_khz = 757000;
-               ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000;
-               ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000;
+               ranges.writer_wm_sets[0].max_drain_clk_khz = 5000000;
        }
 
+       ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
+       ranges.reader_wm_sets[1].wm_inst = WM_B;
+
+       ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
+       ranges.reader_wm_sets[2].wm_inst = WM_C;
+
+       ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
+       ranges.reader_wm_sets[3].wm_inst = WM_D;
+
        /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
        pp->set_wm_ranges(&pp->pp_smu, &ranges);
 }