drm/amd/amdgpu: Tidy up register list formatting.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7c06d1b99d9989861b516bfc17336934feca57a6..8b31f8427d9aa0c04a26d32f5114c574c432251c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -66,38 +66,70 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
 
 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 {
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
-       {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
-               SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
+       { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
+         SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
 };
 
 static const u32 golden_settings_gc_9_0[] =