drm/i915: fix whitelist selftests with readonly registers
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Sat, 29 Jun 2019 13:13:50 +0000 (14:13 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 2 Jul 2019 11:15:19 +0000 (12:15 +0100)
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.

For PS_INVOCATION_COUNT we've got the following piglit tests :

   KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations

Vulkan CTS tests :

   dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*

v2: Use a local to shrink under 80cols.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context registers")
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190629131350.31185-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/selftest_workarounds.c

index f12cb20fe785c1380ee8cb0f93b4dfdac593396a..b933d831eeb184761f0287a75c57fbb00a7569eb 100644 (file)
@@ -926,7 +926,12 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
 
        err = 0;
        for (i = 0; i < engine->whitelist.count; i++) {
-               if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
+               const struct i915_wa *wa = &engine->whitelist.list[i];
+
+               if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
+                       continue;
+
+               if (!fn(engine, a[i], b[i], wa->reg))
                        err = -EINVAL;
        }