clk: rockchip: add flags for rk3328 dclk_lcdc

dclk_lcdc can be sourced from a general pll source as well
as the hdmiphy's pll output. We will want to set this source
by hand (to the system-pll-source in most cases) and also
want rate changes to this clock to be able to also touch
the pll source clock if needed, so add CLK_SET_RATE_PARENT
and CLK_SET_RATE_NO_REPARENT for dclk_lcdc.

Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
[ammended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 983ad5760ce04e503a8eb3be5c2b9dd1d62793ab..f680b421b6d562588df85e9a4d7a16e175451428 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
                        RK3328_CLKGATE_CON(5), 6, GFLAGS),
        DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
                        RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
-       MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, 0,
+       MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
                        RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
 
        /*