drm: bridge: thc63: Restrict modes based on hardware operating frequency

The THC63LVD1024 is restricted to a pixel clock frequency in the range
of 8 to 135 MHz. Implement the bridge .mode_valid() operation
accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>

diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c
index c8b9edd5a7f41309c26f030022e1227273fd2d4a..b083a740565ca44f73fb1029d43113129409473d 100644 (file)
--- a/drivers/gpu/drm/bridge/thc63lvd1024.c
+++ b/drivers/gpu/drm/bridge/thc63lvd1024.c
@@ -45,6 +45,23 @@ static int thc63_attach(struct drm_bridge *bridge)
        return drm_bridge_attach(bridge->encoder, thc63->next, bridge);
 }
 
+static enum drm_mode_status thc63_mode_valid(struct drm_bridge *bridge,
+                                       const struct drm_display_mode *mode)
+{
+       /*
+        * The THC63LVD1024 clock frequency range is 8 to 135 MHz in single-in
+        * mode. Note that the limits are different in dual-in, single-out mode,
+        * and will need to be adjusted accordingly.
+        */
+       if (mode->clock < 8000)
+               return MODE_CLOCK_LOW;
+
+       if (mode->clock > 135000)
+               return MODE_CLOCK_HIGH;
+
+       return MODE_OK;
+}
+
 static void thc63_enable(struct drm_bridge *bridge)
 {
        struct thc63_dev *thc63 = to_thc63(bridge);
@@ -77,6 +94,7 @@ static void thc63_disable(struct drm_bridge *bridge)
 
 static const struct drm_bridge_funcs thc63_bridge_func = {
        .attach = thc63_attach,
+       .mode_valid = thc63_mode_valid,
        .enable = thc63_enable,
        .disable = thc63_disable,
 };