ARM: dts: imx6qdl-udoo: disable AC'97 input pins pad drivers

AC'97 interface RXD and TXC pins are only used as SoC inputs, let's disable
pad drivers for them so we will be protected if, for example, TCLKDIR is
set by mistake in AUDMUX and causes TXC pin to be configured as an output.

This also changes pull direction on these pins from pull-up to pull-down
to match what the board AC'97 CODEC chip (VT1613) has on these pins.

Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index c96c91d83678511478650b87afaeb33a7e0f9f40..839282c55701550c813d90f8cbe34880a334973c 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -208,8 +208,8 @@
                        fsl,pins = <
                                MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x1b0b0
                                MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x1b0b0
-                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x1b0b0
-                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x1b0b0
+                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x13080
+                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x13080
                                MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
                        >;
                };
@@ -218,8 +218,8 @@
                        fsl,pins = <
                                MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x1b0b0
                                MX6QDL_PAD_DI0_PIN3__GPIO4_IO19         0x1b0b0
-                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x1b0b0
-                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x1b0b0
+                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x13080
+                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x13080
                                MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
                        >;
                };
@@ -228,8 +228,8 @@
                        fsl,pins = <
                                MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
                                MX6QDL_PAD_DI0_PIN3__GPIO4_IO19         0x1b0b0
-                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x1b0b0
-                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x1b0b0
+                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x13080
+                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x13080
                                MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
                        >;
                };