drm/meson: Fix an Alpha Primary Plane bug on Meson GXL/GXM SoCs

On the Amlogic GXL & GXM SoCs, a bug occurs on the primary plane when
alpha is used where the alpha is not aligned with the pixel content.

The workaround Amlogic implemented is to reset the OSD1 plane hardware
block each time the plane is (re)enabled, solving the issue.

In the reset, we still need to save the content of 2 registers which
depends on the status of the plane, in addition to reload the scaler
conversion matrix at the same time.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Maxime Jourdan <mjourdan@baylibre.com>
Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20181128100734.6536-1-narmstrong@baylibre.com

diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index 8ee2cf9e47cdc020dfbdbe978725c38645874c0f..6119a02242788e051905251920ace61aa9b23df1 100644 (file)
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -80,6 +80,7 @@
 struct meson_plane {
        struct drm_plane base;
        struct meson_drm *priv;
+       bool enabled;
 };
 #define to_meson_plane(x) container_of(x, struct meson_plane, base)
 
@@ -304,6 +305,15 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
        priv->viu.osd1_stride = fb->pitches[0];
        priv->viu.osd1_height = fb->height;
 
+       if (!meson_plane->enabled) {
+               /* Reset OSD1 before enabling it on GXL+ SoCs */
+               if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
+                   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
+                       meson_viu_osd1_reset(priv);
+
+               meson_plane->enabled = true;
+       }
+
        spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 }
 
@@ -317,6 +327,8 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
        writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
                            priv->io_base + _REG(VPP_MISC));
 
+       meson_plane->enabled = false;
+
 }
 
 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {

diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index 2dffb987ec6573cd4145b51ae5d0ceb8654bb3dc..0ba87ff955302b8599056b98631427f99f711afc 100644 (file)
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -296,6 +296,33 @@ static void meson_viu_load_matrix(struct meson_drm *priv)
                                 true);
 }
 
+/* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */
+void meson_viu_osd1_reset(struct meson_drm *priv)
+{
+       uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2;
+
+       /* Save these 2 registers state */
+       osd1_fifo_ctrl_stat = readl_relaxed(
+                               priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
+       osd1_ctrl_stat2 = readl_relaxed(
+                               priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
+
+       /* Reset OSD1 */
+       writel_bits_relaxed(BIT(0), BIT(0),
+                           priv->io_base + _REG(VIU_SW_RESET));
+       writel_bits_relaxed(BIT(0), 0,
+                           priv->io_base + _REG(VIU_SW_RESET));
+
+       /* Rewrite these registers state lost in the reset */
+       writel_relaxed(osd1_fifo_ctrl_stat,
+                      priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
+       writel_relaxed(osd1_ctrl_stat2,
+                      priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
+
+       /* Reload the conversion matrix */
+       meson_viu_load_matrix(priv);
+}
+
 void meson_viu_init(struct meson_drm *priv)
 {
        uint32_t reg;

diff --git a/drivers/gpu/drm/meson/meson_viu.h b/drivers/gpu/drm/meson/meson_viu.h
index 073b1910bd1b7326a0a57b7f31b8df037c443b18..0f84bddd2ff0ea7b9ec31870d25b94156146b98d 100644 (file)
--- a/drivers/gpu/drm/meson/meson_viu.h
+++ b/drivers/gpu/drm/meson/meson_viu.h
@@ -59,6 +59,7 @@
 #define OSD_REPLACE_EN         BIT(14)
 #define OSD_REPLACE_SHIFT      6
 
+void meson_viu_osd1_reset(struct meson_drm *priv);
 void meson_viu_init(struct meson_drm *priv);
 
 #endif /* __MESON_VIU_H */