drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registers

Each ring has a NOPID register and currently they are regarded as default
value of force_to_nonpriv registers in guest drivers

Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 9ec2cd982705e43d451be0f080ddd8fbf154b896..737cc824344def3e521a23c5f88d7cdf4311efbb 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -817,8 +817,15 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 {
        struct intel_gvt *gvt = s->vgpu->gvt;
        unsigned int data = cmd_val(s, index + 1);
+       u32 ring_base;
+       u32 nopid;
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+
+       ring_base = dev_priv->engine[s->ring_id]->mmio_base;
+       nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 
-       if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
+       if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
+                       data != nopid) {
                gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
                        offset, data);
                return -EPERM;

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 26c924bd7b216ad1b77baae7a6bcce5e953b7755..bf2fa606afcdf185d4836a87651ab4e22df3eb05 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -474,21 +474,27 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
        unsigned int offset, void *p_data, unsigned int bytes)
 {
        u32 reg_nonpriv = *(u32 *)p_data;
+       int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
+       u32 ring_base;
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
        int ret = -EINVAL;
 
-       if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
-               gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
-                       vgpu->id, offset, bytes);
+       if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
+               gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
+                       vgpu->id, ring_id, offset, bytes);
                return ret;
        }
 
-       if (in_whitelist(reg_nonpriv)) {
+       ring_base = dev_priv->engine[ring_id]->mmio_base;
+
+       if (in_whitelist(reg_nonpriv) ||
+               reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
                ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
                        bytes);
-       } else {
-               gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
-                       vgpu->id, reg_nonpriv);
-       }
+       } else
+               gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
+                       vgpu->id, reg_nonpriv, offset);
+
        return ret;
 }