0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
- nor@0 {
+ nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
- nand@100000000 {
+ nand@1,0 {
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
};
- fpga: board-control@200000000 {
+ fpga: board-control@2,0 {
compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
0x1 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
- nor@0 {
+ nor@0,0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
device-width = <1>;
};
- nand@100000000 {
+ nand@1,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
- cpld: board-control@200000000 {
+ cpld: board-control@2,0 {
compatible = "fsl,ls1043ardb-cpld";
reg = <0x2 0x0 0x0000100>;
};
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
- nor@0 {
+ nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
- nand@100000000 {
+ nand@1,0 {
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
};
- fpga: board-control@200000000 {
+ fpga: board-control@2,0 {
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
- nand@0 {
+ nand@0,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x10000>;
};
- cpld: board-control@200000000 {
+ cpld: board-control@2,0 {
compatible = "fsl,ls1046ardb-cpld";
reg = <0x2 0x0 0x0000100>;
};
3 0 0x5 0x20000000 0x00010000>;
status = "okay";
- nor@0 {
+ nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
- nand@200000000 {
+ nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
- fpga: board-control@300000000 {
+ fpga: board-control@3,0 {
compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
reg = <0x3 0x0 0x0000100>;
};
2 0 0x5 0x20000000 0x00010000>;
status = "okay";
- nand@0 {
+ nand@0,0 {
compatible = "fsl,ifc-nand";
reg = <0x0 0x0 0x10000>;
};
- fpga: board-control@200000000 {
+ fpga: board-control@2,0 {
compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
- nor@0 {
+ nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
device-width = <1>;
};
- nand@200000000 {
+ nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
- cpld@300000000 {
+ cpld@3,0 {
reg = <0x3 0x0 0x10000>;
compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
};