struct rtmdio_config {
int cpu_port;
int raw_page;
- int (*read_mmd_phy)(u32 port, u32 addr, u32 reg, u32 *val);
- int (*read_phy)(u32 port, u32 page, u32 reg, u32 *val);
+ int (*read_mmd_phy)(struct mii_bus *bus, u32 port, u32 addr, u32 reg, u32 *val);
+ int (*read_phy)(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val);
int (*reset)(struct mii_bus *bus);
- int (*write_mmd_phy)(u32 port, u32 addr, u32 reg, u32 val);
- int (*write_phy)(u32 port, u32 page, u32 reg, u32 val);
+ int (*write_mmd_phy)(struct mii_bus *bus, u32 port, u32 addr, u32 reg, u32 val);
+ int (*write_phy)(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val);
};
struct rtmdio_phy_info {
}
/* Reads a register in a page from the PHY */
-static int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
{
u32 park_page = 0x1f;
int err;
}
/* Write to a register in a page of the PHY */
-static int rtmdio_838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
{
u32 park_page = 0x1f;
}
/* Read an mmd register of a PHY */
-static int rtmdio_838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
+static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 addr, u32 reg, u32 *val)
{
int err;
}
/* Write to an mmd register of a PHY */
-static int rtmdio_838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
+static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 addr, u32 reg, u32 val)
{
sw_w32(1 << port, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0);
sw_w32_mask(0xffff0000, val << 16, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2);
RTMDIO_839X_PHYREG_ACCESS_CTRL, RTMDIO_839X_CMD_FAIL);
}
-static int rtmdio_839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
{
int err;
u32 v;
return err;
}
-static int rtmdio_839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
{
u32 v;
}
/* Read an mmd register of the PHY */
-static int rtmdio_839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
{
int err;
}
/* Write to an mmd register of the PHY */
-static int rtmdio_839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
{
sw_w32(BIT_ULL(port), RTMDIO_839X_PHYREG_PORT_CTRL);
sw_w32(BIT_ULL(port) >> 32, RTMDIO_839X_PHYREG_PORT_CTRL + 4);
RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_930X_CMD_FAIL);
}
-static int rtmdio_930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
{
u32 v;
return rtmdio_930x_run_cmd(RTMDIO_930X_CMD_WRITE_C22);
}
-static int rtmdio_930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
{
int err;
u32 v;
}
/* Write to an mmd register of the PHY */
-static int rtmdio_930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_930x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
{
sw_w32(BIT(port), RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0);
sw_w32_mask(0xffff << 16, val << 16, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2);
}
/* Read an mmd register of the PHY */
-static int rtmdio_930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_930x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
{
int err ;
RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, RTMDIO_931X_CMD_FAIL);
}
-static int rtmdio_931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
{
sw_w32(0, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2);
sw_w32(0, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
return rtmdio_931x_run_cmd(RTMDIO_931X_CMD_WRITE_C22);
}
-static int rtmdio_931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
{
int err;
}
/* Read an mmd register of the PHY */
-static int rtmdio_931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
{
int err;
}
/* Write to an mmd register of the PHY */
-static int rtmdio_931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
{
u64 mask = BIT_ULL(port);
if (addr >= ctrl->cfg->cpu_port)
return -ENODEV;
- err = (*ctrl->cfg->read_mmd_phy)(addr, devnum, regnum, &val);
+ err = (*ctrl->cfg->read_mmd_phy)(bus, addr, devnum, regnum, &val);
pr_debug("rd_MMD(adr=%d, dev=%d, reg=%d) = %d, err = %d\n",
addr, devnum, regnum, val, err);
return err ? err : val;
ctrl->raw[addr] = (ctrl->page[addr] == ctrl->cfg->raw_page);
- err = (*ctrl->cfg->read_phy)(addr, ctrl->page[addr], regnum, &val);
+ err = (*ctrl->cfg->read_phy)(bus, addr, ctrl->page[addr], regnum, &val);
pr_debug("rd_PHY(adr=%d, pag=%d, reg=%d) = %d, err = %d\n",
addr, ctrl->page[addr], regnum, val, err);
return err ? err : val;
if (addr >= ctrl->cfg->cpu_port)
return -ENODEV;
- err = (*ctrl->cfg->write_mmd_phy)(addr, devnum, regnum, val);
+ err = (*ctrl->cfg->write_mmd_phy)(bus, addr, devnum, regnum, val);
pr_debug("wr_MMD(adr=%d, dev=%d, reg=%d, val=%d) err = %d\n",
addr, devnum, regnum, val, err);
return err;
if (!ctrl->raw[addr] && (regnum != RTMDIO_PAGE_SELECT || page == ctrl->cfg->raw_page)) {
ctrl->raw[addr] = (page == ctrl->cfg->raw_page);
- err = (*ctrl->cfg->write_phy)(addr, page, regnum, val);
+ err = (*ctrl->cfg->write_phy)(bus, addr, page, regnum, val);
pr_debug("wr_PHY(adr=%d, pag=%d, reg=%d, val=%d) err = %d\n",
addr, page, regnum, val, err);
return err;