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drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()
author
Tom St Denis
<tom.stdenis@amd.com>
Wed, 5 Apr 2017 13:16:01 +0000
(09:16 -0400)
committer
Alex Deucher
<alexander.deucher@amd.com>
Thu, 6 Apr 2017 17:27:26 +0000
(13:27 -0400)
Use new WREG32_FIELD15 macro
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index eed149afad224924e209116dca316365f2078519..c386e8b8711f19368070c2176bfe2590f0b6f100 100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@
-1288,9
+1288,7
@@
static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
u32 tmp;
int i;
- tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
- tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
+ WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
gfx_v9_0_tiling_mode_table_init(adev);