drm/amd/powerplay: avoid double check feature enabled

the unforce_dpm_levels doesn't need to check feature enablement.
because the smu_get_dpm_freq_range function has check feature logic.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index e25c1e3094efe5f3c1cfd4dbdc242e0495e4fc0f..3e5d5f359c118c41b3810ccf21fbd5d19d79196f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -833,27 +833,20 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
        return ret;
 }
 
-static int navi10_unforce_dpm_levels(struct smu_context *smu) {
-
+static int navi10_unforce_dpm_levels(struct smu_context *smu)
+{
        int ret = 0, i = 0;
        uint32_t min_freq, max_freq;
        enum smu_clk_type clk_type;
 
-       struct clk_feature_map {
-               enum smu_clk_type clk_type;
-               uint32_t        feature;
-       } clk_feature_map[] = {
-               {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
-               {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
-               {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
+       enum smu_clk_type clks[] = {
+               SMU_GFXCLK,
+               SMU_MCLK,
+               SMU_SOCCLK,
        };
 
-       for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
-               if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
-                       continue;
-
-               clk_type = clk_feature_map[i].clk_type;
-
+       for (i = 0; i < ARRAY_SIZE(clks); i++) {
+               clk_type = clks[i];
                ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;