drm/amdgpu: remove duplicate cg/pg wrapper functions

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 0193f6ced00be025372e5a5e27c9b8ec1425b42f..3000c4abe34fb4edce3c529c45a886198bc70dd6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -222,10 +222,10 @@ enum amdgpu_kiq_irq {
        AMDGPU_CP_KIQ_IRQ_LAST
 };
 
-int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_clockgating_state(void *dev,
                                           enum amd_ip_block_type block_type,
                                           enum amd_clockgating_state state);
-int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_powergating_state(void *dev,
                                           enum amd_ip_block_type block_type,
                                           enum amd_powergating_state state);
 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index dc28fa63bf51ab66cff9ea78dd77e7ca4c5fff11..a8a942c60ea24444c81d7d239c6c4f39dd25a25a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -108,48 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
        WARN(1, "Invalid indirect register space");
 }
 
-static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
-                                 enum amd_ip_block_type block_type,
-                                 enum amd_clockgating_state state)
-{
-       CGS_FUNC_ADEV;
-       int i, r = -1;
-
-       for (i = 0; i < adev->num_ip_blocks; i++) {
-               if (!adev->ip_blocks[i].status.valid)
-                       continue;
-
-               if (adev->ip_blocks[i].version->type == block_type) {
-                       r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
-                                                               (void *)adev,
-                                                                       state);
-                       break;
-               }
-       }
-       return r;
-}
-
-static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
-                                 enum amd_ip_block_type block_type,
-                                 enum amd_powergating_state state)
-{
-       CGS_FUNC_ADEV;
-       int i, r = -1;
-
-       for (i = 0; i < adev->num_ip_blocks; i++) {
-               if (!adev->ip_blocks[i].status.valid)
-                       continue;
-
-               if (adev->ip_blocks[i].version->type == block_type) {
-                       r = adev->ip_blocks[i].version->funcs->set_powergating_state(
-                                                               (void *)adev,
-                                                                       state);
-                       break;
-               }
-       }
-       return r;
-}
-
 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
 {
        CGS_FUNC_ADEV;
@@ -490,8 +448,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
        .read_ind_register = amdgpu_cgs_read_ind_register,
        .write_ind_register = amdgpu_cgs_write_ind_register,
        .get_firmware_info = amdgpu_cgs_get_firmware_info,
-       .set_powergating_state = amdgpu_cgs_set_powergating_state,
-       .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
 };
 
 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 34af664b9f93cd9a4ca87ef7d9da8b0aeb5c9dd8..a53926580b3d0329fbe4a3bddbe973e6f2bb7e70 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,10 +1039,11 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
  * the hardware IP specified.
  * Returns the error code from the last instance.
  */
-int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_clockgating_state(void *dev,
                                           enum amd_ip_block_type block_type,
                                           enum amd_clockgating_state state)
 {
+       struct amdgpu_device *adev = dev;
        int i, r = 0;
 
        for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1072,10 +1073,11 @@ int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
  * the hardware IP specified.
  * Returns the error code from the last instance.
  */
-int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_powergating_state(void *dev,
                                           enum amd_ip_block_type block_type,
                                           enum amd_powergating_state state)
 {
+       struct amdgpu_device *adev = dev;
        int i, r = 0;
 
        for (i = 0; i < adev->num_ip_blocks; i++) {

diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index cab34a4b65ccb228361bd806bb62f3db41048e88..a69deb3a2ac07a8b3e0db851dc0ccdec6b00d351 100644 (file)
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -42,20 +42,6 @@ enum cgs_ind_reg {
        CGS_IND_REG__AUDIO_ENDPT
 };
 
-/**
- * enum cgs_engine - Engines that can be statically power-gated
- */
-enum cgs_engine {
-       CGS_ENGINE__UVD,
-       CGS_ENGINE__VCE,
-       CGS_ENGINE__VP8,
-       CGS_ENGINE__ACP_DMA,
-       CGS_ENGINE__ACP_DSP0,
-       CGS_ENGINE__ACP_DSP1,
-       CGS_ENGINE__ISP,
-       /* ... */
-};
-
 /*
  * enum cgs_ucode_id - Firmware types for different IPs
  */
@@ -152,15 +138,6 @@ typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
                                     enum cgs_ucode_id type,
                                     struct cgs_firmware_info *info);
 
-
-typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
-                                 enum amd_ip_block_type block_type,
-                                 enum amd_powergating_state state);
-
-typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
-                                 enum amd_ip_block_type block_type,
-                                 enum amd_clockgating_state state);
-
 struct cgs_ops {
        /* MMIO access */
        cgs_read_register_t read_register;
@@ -169,9 +146,6 @@ struct cgs_ops {
        cgs_write_ind_register_t write_ind_register;
        /* Firmware Info */
        cgs_get_firmware_info get_firmware_info;
-       /* cg pg interface*/
-       cgs_set_powergating_state set_powergating_state;
-       cgs_set_clockgating_state set_clockgating_state;
 };
 
 struct cgs_os_ops; /* To be define in OS-specific CGS header */
@@ -200,10 +174,5 @@ struct cgs_device
 
 #define cgs_get_firmware_info(dev, type, info) \
        CGS_CALL(get_firmware_info, dev, type, info)
-#define cgs_set_powergating_state(dev, block_type, state)      \
-       CGS_CALL(set_powergating_state, dev, block_type, state)
-#define cgs_set_clockgating_state(dev, block_type, state)      \
-       CGS_CALL(set_clockgating_state, dev, block_type, state)
-
 
 #endif /* _CGS_COMMON_H */

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 1ca6a13be6a3c219c19f59b20d8c23455b961adf..66c49b89cdb4179e524865b0f76753328a5973d9 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -288,10 +288,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
                if (*level & profile_mode_mask) {
                        hwmgr->saved_dpm_level = hwmgr->dpm_level;
                        hwmgr->en_umd_pstate = true;
-                       cgs_set_clockgating_state(hwmgr->device,
+                       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_GFX,
                                                AMD_CG_STATE_UNGATE);
-                       cgs_set_powergating_state(hwmgr->device,
+                       amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_GFX,
                                        AMD_PG_STATE_UNGATE);
                }
@@ -301,10 +301,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
                        if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
                                *level = hwmgr->saved_dpm_level;
                        hwmgr->en_umd_pstate = false;
-                       cgs_set_clockgating_state(hwmgr->device,
+                       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_GFX,
                                        AMD_CG_STATE_GATE);
-                       cgs_set_powergating_state(hwmgr->device,
+                       amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_GFX,
                                        AMD_PG_STATE_GATE);
                }

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index f4cbaee4e2ca6a97ab87039b88c75c256590f88e..6d72a5600917c48d038da97a01c9d52e1f1e2985 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -147,20 +147,20 @@ void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
        data->uvd_power_gated = bgate;
 
        if (bgate) {
-               cgs_set_powergating_state(hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_PG_STATE_GATE);
-               cgs_set_clockgating_state(hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                AMD_IP_BLOCK_TYPE_UVD,
                                AMD_CG_STATE_GATE);
                smu7_update_uvd_dpm(hwmgr, true);
                smu7_powerdown_uvd(hwmgr);
        } else {
                smu7_powerup_uvd(hwmgr);
-               cgs_set_clockgating_state(hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                AMD_IP_BLOCK_TYPE_UVD,
                                AMD_CG_STATE_UNGATE);
-               cgs_set_powergating_state(hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_PG_STATE_UNGATE);
                smu7_update_uvd_dpm(hwmgr, false);
@@ -175,20 +175,20 @@ void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
        data->vce_power_gated = bgate;
 
        if (bgate) {
-               cgs_set_powergating_state(hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_VCE,
                                                AMD_PG_STATE_GATE);
-               cgs_set_clockgating_state(hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                AMD_IP_BLOCK_TYPE_VCE,
                                AMD_CG_STATE_GATE);
                smu7_update_vce_dpm(hwmgr, true);
                smu7_powerdown_vce(hwmgr);
        } else {
                smu7_powerup_vce(hwmgr);
-               cgs_set_clockgating_state(hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                AMD_IP_BLOCK_TYPE_VCE,
                                AMD_CG_STATE_UNGATE);
-               cgs_set_powergating_state(hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_VCE,
                                                AMD_PG_STATE_UNGATE);
                smu7_update_vce_dpm(hwmgr, false);

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index c2f93aa1d2e8cad29606fb737b0a52997d124971..50690c72b2ea1ea816a5de9149a45079ec059257 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1892,20 +1892,20 @@ static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
        data->uvd_power_gated = bgate;
 
        if (bgate) {
-               cgs_set_powergating_state(hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_PG_STATE_GATE);
-               cgs_set_clockgating_state(hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_CG_STATE_GATE);
                smu8_dpm_update_uvd_dpm(hwmgr, true);
                smu8_dpm_powerdown_uvd(hwmgr);
        } else {
                smu8_dpm_powerup_uvd(hwmgr);
-               cgs_set_clockgating_state(hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_CG_STATE_UNGATE);
-               cgs_set_powergating_state(hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_PG_STATE_UNGATE);
                smu8_dpm_update_uvd_dpm(hwmgr, false);
@@ -1918,12 +1918,10 @@ static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
        struct smu8_hwmgr *data = hwmgr->backend;
 
        if (bgate) {
-               cgs_set_powergating_state(
-                                       hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_VCE,
                                        AMD_PG_STATE_GATE);
-               cgs_set_clockgating_state(
-                                       hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_VCE,
                                        AMD_CG_STATE_GATE);
                smu8_enable_disable_vce_dpm(hwmgr, false);
@@ -1932,12 +1930,10 @@ static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
        } else {
                smu8_dpm_powerup_vce(hwmgr);
                data->vce_power_gated = false;
-               cgs_set_clockgating_state(
-                                       hwmgr->device,
+               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_VCE,
                                        AMD_CG_STATE_UNGATE);
-               cgs_set_powergating_state(
-                                       hwmgr->device,
+               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
                                        AMD_IP_BLOCK_TYPE_VCE,
                                        AMD_PG_STATE_UNGATE);
                smu8_dpm_update_vce_dpm(hwmgr);

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index d023494c3eae25fc459ec826e525e342489554b9..dae3422366b3ab9890d37217a5a63e9bc37d028c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -306,13 +306,13 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
        }
 
        /* To initialize all clock gating before RLC loaded and running.*/
-       cgs_set_clockgating_state(hwmgr->device,
+       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                        AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
-       cgs_set_clockgating_state(hwmgr->device,
+       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                        AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
-       cgs_set_clockgating_state(hwmgr->device,
+       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                        AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
-       cgs_set_clockgating_state(hwmgr->device,
+       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
                        AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
 
        /* Setup SoftRegsStart here for register lookup in case