drm/amd/display: Add override for reporting wm ranges

For verification of watermark select with SMU team, proper
implementation will follow

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9337ccadc32115ad6312e5ddd8c4100947d5d31f..6318f9f69c928faf067a3353827c4b051c07126d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1441,6 +1441,53 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
        ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz;
        ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz;
 
+       if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
+               ranges.reader_wm_sets[0].wm_inst = WM_A;
+               ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;
+               ranges.reader_wm_sets[0].max_drain_clk_khz = 654000;
+               ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;
+               ranges.reader_wm_sets[0].max_fill_clk_khz = 800000;
+               ranges.writer_wm_sets[0].wm_inst = WM_A;
+               ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;
+               ranges.writer_wm_sets[0].max_fill_clk_khz = 757000;
+               ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;
+               ranges.writer_wm_sets[0].max_drain_clk_khz = 800000;
+
+               ranges.reader_wm_sets[1].wm_inst = WM_B;
+               ranges.reader_wm_sets[1].min_drain_clk_khz = 300000;
+               ranges.reader_wm_sets[1].max_drain_clk_khz = 654000;
+               ranges.reader_wm_sets[1].min_fill_clk_khz = 933000;
+               ranges.reader_wm_sets[1].max_fill_clk_khz = 933000;
+               ranges.writer_wm_sets[1].wm_inst = WM_B;
+               ranges.writer_wm_sets[1].min_fill_clk_khz = 200000;
+               ranges.writer_wm_sets[1].max_fill_clk_khz = 757000;
+               ranges.writer_wm_sets[1].min_drain_clk_khz = 933000;
+               ranges.writer_wm_sets[1].max_drain_clk_khz = 933000;
+
+
+               ranges.reader_wm_sets[2].wm_inst = WM_C;
+               ranges.reader_wm_sets[2].min_drain_clk_khz = 300000;
+               ranges.reader_wm_sets[2].max_drain_clk_khz = 654000;
+               ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000;
+               ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000;
+               ranges.writer_wm_sets[2].wm_inst = WM_C;
+               ranges.writer_wm_sets[2].min_fill_clk_khz = 200000;
+               ranges.writer_wm_sets[2].max_fill_clk_khz = 757000;
+               ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000;
+               ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000;
+
+               ranges.reader_wm_sets[3].wm_inst = WM_D;
+               ranges.reader_wm_sets[3].min_drain_clk_khz = 300000;
+               ranges.reader_wm_sets[3].max_drain_clk_khz = 654000;
+               ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000;
+               ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000;
+               ranges.writer_wm_sets[3].wm_inst = WM_D;
+               ranges.writer_wm_sets[3].min_fill_clk_khz = 200000;
+               ranges.writer_wm_sets[3].max_fill_clk_khz = 757000;
+               ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000;
+               ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000;
+       }
+
        /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
        pp->set_wm_ranges(&pp->pp_smu, &ranges);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index dbbe1d621bee21b58b5962f70f38c0a5a1b85919..d624554efbc7c83a3be4228bbcf7406659d88fc4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -173,6 +173,11 @@ enum pipe_split_policy {
        MPC_SPLIT_AVOID_MULT_DISP = 2,
 };
 
+enum wm_report_mode {
+       WM_REPORT_DEFAULT = 0,
+       WM_REPORT_OVERRIDE = 1,
+};
+
 struct dc_debug {
        bool surface_visual_confirm;
        bool sanity_checks;
@@ -194,6 +199,7 @@ struct dc_debug {
        bool disable_dpp_power_gate;
        bool disable_hubp_power_gate;
        bool disable_pplib_wm_range;
+       enum wm_report_mode pplib_wm_report_mode;
        bool use_dml_wm;
        unsigned int min_disp_clk_khz;
        int sr_exit_time_dpm0_ns;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index efa3f6f97bafb3f2abe805e3ea651d12a177de39..86cfab33feea84474170f0b0bf7e8c820575e1c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2451,6 +2451,9 @@ static void optimize_shared_resources(struct dc *dc)
                /* S0i2 message */
                dcn10_pplib_apply_display_requirements(dc, dc->current_state);
        }
+
+       if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
+               dcn_bw_notify_pplib_of_wm_ranges(dc);
 }
 
 static void ready_shared_resources(struct dc *dc, struct dc_state *context)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4018e831eb4baafe13529c0a489f3cd53dd01117..5d618e68a744d6060c91319c840dedfb4bc19030 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -424,6 +424,7 @@ static const struct dc_debug debug_defaults_drv = {
 
                .disable_pplib_clock_request = true,
                .disable_pplib_wm_range = false,
+               .pplib_wm_report_mode = WM_REPORT_DEFAULT,
                .use_dml_wm = false,
 
                .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,