ASoC: TWL6040: Fix playback with 19.2 Mhz MCLK

When using MCLK is configured for 19.2 Mhz, clock slicer should be
enabled and HPPLL should be bypassed in clock path.

Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>

diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index af36346ff3364bdb37b93b620e3cae6f4fbc6444..85dd4fb4c68173960b698197c44e8a395f7907c8 100644 (file)
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -928,7 +928,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
                case 19200000:
                        /* mclk input, pll disabled */
                        hppllctl |= TWL6040_MCLK_19200KHZ |
-                                   TWL6040_HPLLSQRBP |
+                                   TWL6040_HPLLSQRENA |
                                    TWL6040_HPLLBP;
                        break;
                case 26000000: