}
static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
- unsigned reg, u32 val)
+ unsigned reg, u32 val)
{
writel(val, hsdma->base + reg);
}
static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
chan->tx_idx = 0;
chan->rx_idx = HSDMA_DESCS_NUM - 1;
}
static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
struct hsdma_desc *tx_desc;
struct hsdma_desc *rx_desc;
}
static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
int i;
}
static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
dma_addr_t src, dst;
size_t len, tlen;
}
static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
struct mtk_hsdma_desc *desc;
int chan_issued;
tasklet_schedule(&hsdma->task);
else
dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n",
- status);
+ status);
/* clean intr bits */
mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
}
static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
- dma_cookie_t cookie, struct dma_tx_state *state)
+ dma_cookie_t cookie,
+ struct dma_tx_state *state)
{
return dma_cookie_status(c, cookie, state);
}
}
static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
int i;
}
static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
- struct mtk_hsdma_chan *chan)
+ struct mtk_hsdma_chan *chan)
{
if (chan->tx_ring) {
dma_free_coherent(hsdma->ddev.dev,
/* hardware info */
reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
- (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
- (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
+ (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
+ (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
hsdma_dump_reg(hsdma);
return -EINVAL;
}
ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
- 0, dev_name(&pdev->dev), hsdma);
+ 0, dev_name(&pdev->dev), hsdma);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
ret = of_dma_controller_register(pdev->dev.of_node,
- of_dma_xlate_by_chan_id, hsdma);
+ of_dma_xlate_by_chan_id, hsdma);
if (ret) {
dev_err(&pdev->dev, "failed to register of dma controller\n");
goto err_unregister;
}
static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
- unsigned int reg)
+ unsigned int reg)
{
return readl(dma_dev->base + reg);
}
static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
- unsigned reg, uint32_t val)
+ unsigned reg, uint32_t val)
{
writel(val, dma_dev->base + reg);
}
}
static int gdma_dma_config(struct dma_chan *c,
- struct dma_slave_config *config)
+ struct dma_slave_config *config)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
break;
default:
dev_err(dma_dev->ddev.dev, "direction type %d error\n",
- config->direction);
+ config->direction);
return -EINVAL;
}
GDMA_REG_CTRL0_ENABLE) {
if (time_after_eq(jiffies, timeout)) {
dev_err(dma_dev->ddev.dev, "chan %d wait timeout\n",
- chan->id);
+ chan->id);
/* restore to init value */
gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), 0);
break;
if (i)
dev_dbg(dma_dev->ddev.dev, "terminate chan %d loops %d\n",
- chan->id, i);
+ chan->id, i);
return 0;
}
ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
- chan->id, ctrl0);
+ chan->id, ctrl0);
rt305x_dump_reg(dma_dev, chan->id);
return -EINVAL;
}
(8 << GDMA_REG_CTRL1_DST_REQ_SHIFT);
} else {
dev_err(dma_dev->ddev.dev, "direction type %d error\n",
- chan->desc->direction);
+ chan->desc->direction);
return -EINVAL;
}
ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
- chan->id, ctrl0);
+ chan->id, ctrl0);
rt3883_dump_reg(dma_dev, chan->id);
return -EINVAL;
}
GDMA_REG_CTRL1_COHERENT;
} else {
dev_err(dma_dev->ddev.dev, "direction type %d error\n",
- chan->desc->direction);
+ chan->desc->direction);
return -EINVAL;
}
}
static inline int gdma_start_transfer(struct gdma_dma_dev *dma_dev,
- struct gdma_dmaengine_chan *chan)
+ struct gdma_dmaengine_chan *chan)
{
return dma_dev->data->start_transfer(chan);
}
}
static void gdma_dma_chan_irq(struct gdma_dma_dev *dma_dev,
- struct gdma_dmaengine_chan *chan)
+ struct gdma_dmaengine_chan *chan)
{
struct gdma_dma_desc *desc;
unsigned long flags;
}
} else
dev_dbg(dma_dev->ddev.dev, "chan %d no desc to complete\n",
- chan->id);
+ chan->id);
if (chan_issued)
set_bit(chan->id, &dma_dev->chan_issued);
spin_unlock_irqrestore(&chan->vchan.lock, flags);
tasklet_schedule(&dma_dev->task);
} else
dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n",
- chan->id);
+ chan->id);
}
spin_unlock_irqrestore(&chan->vchan.lock, flags);
}
desc->sg[i].dst_addr = sg_dma_address(sg);
else {
dev_err(c->device->dev, "direction type %d error\n",
- direction);
+ direction);
goto free_desc;
}
if (unlikely(sg_dma_len(sg) > GDMA_REG_CTRL0_TX_MASK)) {
dev_err(c->device->dev, "sg len too large %d\n",
- sg_dma_len(sg));
+ sg_dma_len(sg));
goto free_desc;
}
desc->sg[i].len = sg_dma_len(sg);
if (period_len > GDMA_REG_CTRL0_TX_MASK) {
dev_err(c->device->dev, "cyclic len too large %d\n",
- period_len);
+ period_len);
return NULL;
}
desc->sg[i].dst_addr = buf_addr;
else {
dev_err(c->device->dev, "direction type %d error\n",
- direction);
+ direction);
goto free_desc;
}
desc->sg[i].len = period_len;
}
static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
- dma_cookie_t cookie, struct dma_tx_state *state)
+ dma_cookie_t cookie,
+ struct dma_tx_state *state)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct virt_dma_desc *vdesc;
gct = gdma_dma_read(dma_dev, GDMA_RT305X_GCT);
dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
- (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
- 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
- GDMA_REG_GCT_CHAN_MASK));
+ (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
+ 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
+ GDMA_REG_GCT_CHAN_MASK));
}
static void rt3883_gdma_init(struct gdma_dma_dev *dma_dev)
gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
- (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
- 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
- GDMA_REG_GCT_CHAN_MASK));
+ (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
+ 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
+ GDMA_REG_GCT_CHAN_MASK));
}
static struct gdma_data rt305x_gdma_data = {
return -EINVAL;
}
ret = devm_request_irq(&pdev->dev, irq, gdma_dma_irq,
- 0, dev_name(&pdev->dev), dma_dev);
+ 0, dev_name(&pdev->dev), dma_dev);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
ret = of_dma_controller_register(pdev->dev.of_node,
- of_dma_xlate_by_chan_id, dma_dev);
+ of_dma_xlate_by_chan_id, dma_dev);
if (ret) {
dev_err(&pdev->dev, "failed to register of dma controller\n");
goto err_unregister;