spi: dw: make sure SPI controller is enabled

The error handling is partially broken since the controller is disabled on
error and is not re-enabled until condition occurs, i.e. mode (poll, PIO/DMA),
chip (cs_change), or speed (clk_div) is changed. In the result of these changes
we will have a predictable state of the SPi controller independently on how
successfull was a previous transfer.

The patch disables interrupts and re-enables the SPI controller wherever it
needs to be done. Thus most of the time the SPI controller is kept enabled. The
runtime PM, when it will be implemented, must take care of the controller
disabling and re-enabling.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 281121f001388e7fd38d8dc330480ddd8595fb1c..321965607fc040a02d208dec203bbf38cb6555ee 100644 (file)
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -272,8 +272,7 @@ static void giveback(struct dw_spi *dws)
 
 static void int_error_stop(struct dw_spi *dws, const char *msg)
 {
-       /* Stop the hw */
-       spi_enable_chip(dws, 0);
+       spi_reset_chip(dws);
 
        dev_err(&dws->master->dev, "%s\n", msg);
        dws->cur_msg->state = ERROR_STATE;
@@ -606,9 +605,7 @@ static void dw_spi_cleanup(struct spi_device *spi)
 /* Restart the controller, disable all interrupts, clean rx fifo */
 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 {
-       spi_enable_chip(dws, 0);
-       spi_mask_intr(dws, 0xff);
-       spi_enable_chip(dws, 1);
+       spi_reset_chip(dws);
 
        /*
         * Try to detect the FIFO depth if not set by interface driver,

diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 3d32be68c14210c93e0ae3a6c87e65c7e5c38759..1a7f083c2217dad650b8b5a5abf6302ddcc9ff6e 100644 (file)
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -216,6 +216,18 @@ static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
        dw_writel(dws, DW_SPI_IMR, new_mask);
 }
 
+/*
+ * This does disable the SPI controller, interrupts, and re-enable the
+ * controller back. Transmit and receive FIFO buffers are cleared when the
+ * device is disabled.
+ */
+static inline void spi_reset_chip(struct dw_spi *dws)
+{
+       spi_enable_chip(dws, 0);
+       spi_mask_intr(dws, 0xff);
+       spi_enable_chip(dws, 1);
+}
+
 /*
  * Each SPI slave device to work with dw_api controller should
  * has such a structure claiming its working mode (PIO/DMA etc),