drm/i915: Pass dev_priv to init_clock_gating

Unify our approach to things by passing around dev_priv instead of dev.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477946245-14134-24-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 77ca07f7f94e3e41e5861e78769c5c68f7848fca..f83dde9e36d11df7c9f53176bbb4fb470617ba96 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2264,7 +2264,6 @@ err1:
 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
                                bool rpm_resume)
 {
-       struct drm_device *dev = &dev_priv->drm;
        int err;
        int ret;
 
@@ -2289,7 +2288,7 @@ static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
        vlv_check_no_gt_access(dev_priv);
 
        if (rpm_resume)
-               intel_init_clock_gating(dev);
+               intel_init_clock_gating(dev_priv);
 
        return ret;
 }

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63672c3c1118fbd2fa04249a3b8244f4494a1c71..b8e72cdcb713ab76f7797122cdd7abb67104ede9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -525,7 +525,7 @@ struct drm_i915_display_funcs {
                                   const struct drm_display_mode *adjusted_mode);
        void (*audio_codec_disable)(struct intel_encoder *encoder);
        void (*fdi_link_train)(struct drm_crtc *crtc);
-       void (*init_clock_gating)(struct drm_device *dev);
+       void (*init_clock_gating)(struct drm_i915_private *dev_priv);
        int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
                          struct drm_framebuffer *fb,
                          struct drm_i915_gem_object *obj,

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53e8461585595d5e0de8cce684b352c51a8472c6..a46922aec99bd631158b994ff36e56ca742aa383 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16314,7 +16314,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
 
        dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
 
-       intel_init_clock_gating(dev);
+       intel_init_clock_gating(dev_priv);
 }
 
 /*

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0fdd546ac8d8f4970011cccc989d379c520060c1..3a9ca2755829fbedf75e574c672558500dc4f2d7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1703,7 +1703,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 
 /* intel_pm.c */
-void intel_init_clock_gating(struct drm_device *dev);
+void intel_init_clock_gating(struct drm_i915_private *dev_priv);
 void intel_suspend_hw(struct drm_device *dev);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
 void intel_update_watermarks(struct intel_crtc *crtc);

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cb518c506c67490678631e38e7036456905cf775..3e9bc2ac26b440b5d29a794685034ea849263161 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -56,10 +56,8 @@
 #define INTEL_RC6p_ENABLE                      (1<<1)
 #define INTEL_RC6pp_ENABLE                     (1<<2)
 
-static void gen9_init_clock_gating(struct drm_device *dev)
+static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
        /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
        I915_WRITE(CHICKEN_PAR1_1,
                   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
@@ -82,11 +80,9 @@ static void gen9_init_clock_gating(struct drm_device *dev)
                   ILK_DPFC_DISABLE_DUMMY0);
 }
 
-static void bxt_init_clock_gating(struct drm_device *dev)
+static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
-       gen9_init_clock_gating(dev);
+       gen9_init_clock_gating(dev_priv);
 
        /* WaDisableSDEUnitClockGating:bxt */
        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
@@ -6857,10 +6853,8 @@ void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
        }
 }
 
-static void ibx_init_clock_gating(struct drm_device *dev)
+static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        /*
         * On Ibex Peak and Cougar Point, we need to disable clock
         * gating for the panel power sequencer or it will fail to
@@ -6869,9 +6863,8 @@ static void ibx_init_clock_gating(struct drm_device *dev)
        I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
 }
 
-static void g4x_disable_trickle_feed(struct drm_device *dev)
+static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        enum pipe pipe;
 
        for_each_pipe(dev_priv, pipe) {
@@ -6884,10 +6877,8 @@ static void g4x_disable_trickle_feed(struct drm_device *dev)
        }
 }
 
-static void ilk_init_lp_watermarks(struct drm_device *dev)
+static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
        I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
        I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
@@ -6898,9 +6889,8 @@ static void ilk_init_lp_watermarks(struct drm_device *dev)
         */
 }
 
-static void ironlake_init_clock_gating(struct drm_device *dev)
+static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
 
        /*
@@ -6932,7 +6922,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
                   (I915_READ(DISP_ARB_CTL) |
                    DISP_FBC_WM_DIS));
 
-       ilk_init_lp_watermarks(dev);
+       ilk_init_lp_watermarks(dev_priv);
 
        /*
         * Based on the document from hardware guys the following bits
@@ -6967,14 +6957,13 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
        /* WaDisable_RenderCache_OperationalFlush:ilk */
        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 
-       g4x_disable_trickle_feed(dev);
+       g4x_disable_trickle_feed(dev_priv);
 
-       ibx_init_clock_gating(dev);
+       ibx_init_clock_gating(dev_priv);
 }
 
-static void cpt_init_clock_gating(struct drm_device *dev)
+static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        int pipe;
        uint32_t val;
 
@@ -7009,9 +6998,8 @@ static void cpt_init_clock_gating(struct drm_device *dev)
        }
 }
 
-static void gen6_check_mch_setup(struct drm_device *dev)
+static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        uint32_t tmp;
 
        tmp = I915_READ(MCH_SSKPD);
@@ -7020,9 +7008,8 @@ static void gen6_check_mch_setup(struct drm_device *dev)
                              tmp);
 }
 
-static void gen6_init_clock_gating(struct drm_device *dev)
+static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
 
        I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
@@ -7049,7 +7036,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
        I915_WRITE(GEN6_GT_MODE,
                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
 
-       ilk_init_lp_watermarks(dev);
+       ilk_init_lp_watermarks(dev_priv);
 
        I915_WRITE(CACHE_MODE_0,
                   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
@@ -7110,11 +7097,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
                   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
 
-       g4x_disable_trickle_feed(dev);
+       g4x_disable_trickle_feed(dev_priv);
 
-       cpt_init_clock_gating(dev);
+       cpt_init_clock_gating(dev_priv);
 
-       gen6_check_mch_setup(dev);
+       gen6_check_mch_setup(dev_priv);
 }
 
 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
@@ -7135,10 +7122,8 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
        I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
-static void lpt_init_clock_gating(struct drm_device *dev)
+static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        /*
         * TODO: this bit should only be enabled when really needed, then
         * disabled when not needed anymore in order to save power.
@@ -7189,11 +7174,9 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void kabylake_init_clock_gating(struct drm_device *dev)
+static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       gen9_init_clock_gating(dev);
+       gen9_init_clock_gating(dev_priv);
 
        /* WaDisableSDEUnitClockGating:kbl */
        if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
@@ -7210,11 +7193,9 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
                   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
-static void skylake_init_clock_gating(struct drm_device *dev)
+static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       gen9_init_clock_gating(dev);
+       gen9_init_clock_gating(dev_priv);
 
        /* WAC6entrylatency:skl */
        I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
@@ -7225,12 +7206,11 @@ static void skylake_init_clock_gating(struct drm_device *dev)
                   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
-static void broadwell_init_clock_gating(struct drm_device *dev)
+static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        enum pipe pipe;
 
-       ilk_init_lp_watermarks(dev);
+       ilk_init_lp_watermarks(dev_priv);
 
        /* WaSwitchSolVfFArbitrationPriority:bdw */
        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
@@ -7273,14 +7253,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
        I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
                   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
 
-       lpt_init_clock_gating(dev);
+       lpt_init_clock_gating(dev_priv);
 }
 
-static void haswell_init_clock_gating(struct drm_device *dev)
+static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
-       ilk_init_lp_watermarks(dev);
+       ilk_init_lp_watermarks(dev_priv);
 
        /* L3 caching of data atomics doesn't work -- disable it. */
        I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
@@ -7329,15 +7307,14 @@ static void haswell_init_clock_gating(struct drm_device *dev)
        I915_WRITE(CHICKEN_PAR1_1,
                   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
 
-       lpt_init_clock_gating(dev);
+       lpt_init_clock_gating(dev_priv);
 }
 
-static void ivybridge_init_clock_gating(struct drm_device *dev)
+static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        uint32_t snpcr;
 
-       ilk_init_lp_watermarks(dev);
+       ilk_init_lp_watermarks(dev_priv);
 
        I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
 
@@ -7394,7 +7371,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
                        I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
                        GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-       g4x_disable_trickle_feed(dev);
+       g4x_disable_trickle_feed(dev_priv);
 
        gen7_setup_fixed_func_scheduler(dev_priv);
 
@@ -7425,15 +7402,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
        I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
 
        if (!HAS_PCH_NOP(dev_priv))
-               cpt_init_clock_gating(dev);
+               cpt_init_clock_gating(dev_priv);
 
-       gen6_check_mch_setup(dev);
+       gen6_check_mch_setup(dev_priv);
 }
 
-static void valleyview_init_clock_gating(struct drm_device *dev)
+static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        /* WaDisableEarlyCull:vlv */
        I915_WRITE(_3D_CHICKEN3,
                   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
@@ -7512,10 +7487,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
        I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
-static void cherryview_init_clock_gating(struct drm_device *dev)
+static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        /* WaVSRefCountFullforceMissDisable:chv */
        /* WaDSRefCountFullforceMissDisable:chv */
        I915_WRITE(GEN7_FF_THREAD_MODE,
@@ -7548,9 +7521,8 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
        I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
 }
 
-static void g4x_init_clock_gating(struct drm_device *dev)
+static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        uint32_t dspclk_gate;
 
        I915_WRITE(RENCLK_GATE_D1, 0);
@@ -7572,13 +7544,11 @@ static void g4x_init_clock_gating(struct drm_device *dev)
        /* WaDisable_RenderCache_OperationalFlush:g4x */
        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 
-       g4x_disable_trickle_feed(dev);
+       g4x_disable_trickle_feed(dev_priv);
 }
 
-static void crestline_init_clock_gating(struct drm_device *dev)
+static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
        I915_WRITE(RENCLK_GATE_D2, 0);
        I915_WRITE(DSPCLK_GATE_D, 0);
@@ -7591,10 +7561,8 @@ static void crestline_init_clock_gating(struct drm_device *dev)
        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 }
 
-static void broadwater_init_clock_gating(struct drm_device *dev)
+static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
                   I965_RCC_CLOCK_GATE_DISABLE |
                   I965_RCPB_CLOCK_GATE_DISABLE |
@@ -7608,9 +7576,8 @@ static void broadwater_init_clock_gating(struct drm_device *dev)
        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 }
 
-static void gen3_init_clock_gating(struct drm_device *dev)
+static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        u32 dstate = I915_READ(D_STATE);
 
        dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
@@ -7633,10 +7600,8 @@ static void gen3_init_clock_gating(struct drm_device *dev)
                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
 }
 
-static void i85x_init_clock_gating(struct drm_device *dev)
+static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
 
        /* interrupts should cause a wake up from C3 */
@@ -7647,10 +7612,8 @@ static void i85x_init_clock_gating(struct drm_device *dev)
                   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
 }
 
-static void i830_init_clock_gating(struct drm_device *dev)
+static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 
        I915_WRITE(MEM_MODE,
@@ -7658,11 +7621,9 @@ static void i830_init_clock_gating(struct drm_device *dev)
                   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
 }
 
-void intel_init_clock_gating(struct drm_device *dev)
+void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
-       dev_priv->display.init_clock_gating(dev);
+       dev_priv->display.init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_device *dev)
@@ -7671,7 +7632,7 @@ void intel_suspend_hw(struct drm_device *dev)
                lpt_suspend_hw(dev);
 }
 
-static void nop_init_clock_gating(struct drm_device *dev)
+static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
 }