drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write

GEN7_UCGCTL4 does not live in the context.

v2: Missing parenthesis

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-4-git-send-email-oscar.mateo@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6e24711c106c0f308de0aab1ce390876919d170f..48c7eb36d6331a4eb74ebd15eadd10dd793ce1e8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -981,7 +981,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
                                   GEN9_GAPS_TSV_CREDIT_DISABLE));
 
        /* WaDisableGafsUnitClkGating:skl */
-       WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+       I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+                                 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
 
        /* WaInPlaceDecompressionHang:skl */
        if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
@@ -1143,7 +1144,8 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
                                  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
        /* WaDisableGafsUnitClkGating:kbl */
-       WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+       I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+                                 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
 
        /* WaDisableSbeCacheDispatchPortSharing:kbl */
        WA_SET_BIT_MASKED(
@@ -1197,7 +1199,8 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
                          GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
        /* WaDisableGafsUnitClkGating:cfl */
-       WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+       I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+                                 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
 
        /* WaDisableSbeCacheDispatchPortSharing:cfl */
        WA_SET_BIT_MASKED(