drm/i915/dp: clean up source rate limiting for cnl

Make the limiting rate based instead of messing with the array size.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/cb03b9419191a7d6359bf371aacb2d3725c746de.1517482774.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1d4eced394cf0485adee53ef281f600ba79b14c3..bee51051482677bf8b6c356f7f2daf1bac311df4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -240,7 +240,7 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
        return max_dotclk;
 }
 
-static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
+static int cnl_max_source_rate(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
@@ -250,17 +250,17 @@ static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
 
        /* Low voltage SKUs are limited to max of 5.4G */
        if (voltage == VOLTAGE_INFO_0_85V)
-               return size - 2;
+               return 540000;
 
        /* For this SKU 8.1G is supported in all ports */
        if (IS_CNL_WITH_PORT_F(dev_priv))
-               return size;
+               return 810000;
 
        /* For other SKUs, max rate on ports A and B is 5.4G */
        if (port == PORT_A || port == PORT_D)
-               return size - 2;
+               return 540000;
 
-       return size;
+       return 810000;
 }
 
 static void
@@ -269,7 +269,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        const int *source_rates;
-       int size;
+       int size, max_rate = 0;
 
        /* This should only be done once */
        WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -279,7 +279,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
                size = ARRAY_SIZE(bxt_rates);
        } else if (IS_CANNONLAKE(dev_priv)) {
                source_rates = cnl_rates;
-               size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
+               size = ARRAY_SIZE(cnl_rates);
+               max_rate = cnl_max_source_rate(intel_dp);
        } else if (IS_GEN9_BC(dev_priv)) {
                source_rates = skl_rates;
                size = ARRAY_SIZE(skl_rates);
@@ -292,6 +293,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
                size = ARRAY_SIZE(default_rates) - 1;
        }
 
+       if (max_rate)
+               size = intel_dp_rate_limit_len(source_rates, size, max_rate);
+
        intel_dp->source_rates = source_rates;
        intel_dp->num_source_rates = size;
 }