drm/i915: use the new masked bit macro some more

I've missed this one.

v2: Chris Wilson noticed another register.
v3: Color choice improvements.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0d53eacd293f2993643d136605de5fcd0c01a6d5..b46a3fd1774688e43d08d60774a8170cd3881d8b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3721,12 +3721,8 @@ i915_gem_load(struct drm_device *dev)
 
        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
        if (IS_GEN3(dev)) {
-               u32 tmp = I915_READ(MI_ARB_STATE);
-               if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
-                       /* arb state is a masked write, so set bit + bit in mask */
-                       tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
-                       I915_WRITE(MI_ARB_STATE, tmp);
-               }
+               I915_WRITE(MI_ARB_STATE,
+                          _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
        }
 
        dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1f4d8f1df6a53c36880800465182d7a750a3b71..7bc407a87c0cdb841ebc197c3d30cd0a51875c88 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -570,7 +570,6 @@
 #define LM_BURST_LENGTH     0x00000700
 #define LM_FIFO_WATERMARK   0x0000001F
 #define MI_ARB_STATE   0x020e4 /* 915+ only */
-#define   MI_ARB_MASK_SHIFT      16    /* shift for enable bits */
 
 /* Make render/texture TLB fetches lower priorty than associated data
  *   fetches. This is not turned on by default
@@ -635,7 +634,6 @@
 #define   MI_ARB_DISPLAY_PRIORITY_B_A          (1 << 0)        /* display B > display A */
 
 #define CACHE_MODE_0   0x02120 /* 915+ only */
-#define   CM0_MASK_SHIFT          16
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
 #define   CM0_ZR_OPT_DISABLE      (1<<5)
 #define          CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0552058a202fa0ba037c08e98f3db73cd1f967c4..e66330cc0934240e38b9f3d8c9b1d0dda17e4354 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2663,9 +2663,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
        I915_WRITE(WM2_LP_ILK, 0);
        I915_WRITE(WM1_LP_ILK, 0);
 
-       /* clear masked bit */
        I915_WRITE(CACHE_MODE_0,
-                  CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
+                  _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 
        I915_WRITE(GEN6_UCGCTL1,
                   I915_READ(GEN6_UCGCTL1) |