--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+ model = "Hewlett-Packard MSM460";
+ compatible = "hpe,msm460";
+
+ aliases {
+ led-boot = &system_green;
+ led-failsafe = &system_green;
+ led-running = &system_green;
+ led-upgrade = &system_green;
+ };
+
+ chosen {
+ /* Needed for initramfs */
+ bootargs-override = "console=ttyS0,115200 ubi.mtd=5,2048";
+ stdout-path = &serial0;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = <0 0xffe05000 0 0x1000>;
+ ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+ 0x1 0x0 0x0 0xff800000 0x00040000
+ 0x2 0x0 0x0 0xffa00000 0x00020000
+ 0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+ nand@1,0 {
+ compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0xc0000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ partition@c0000 {
+ reg = <0xc0000 0x40000>;
+ label = "colubris-bid";
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_hwinfo_1f822: macaddr@1f822 {
+ /* ETH */
+ compatible = "mac-base";
+ reg = <0x1f822 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ macaddr_hwinfo_1f9bd: macaddr@1f9bd {
+ /* WLAN */
+ compatible = "mac-base";
+ reg = <0x1f9bd 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ /* uenv{0,1} and ubi occupy kernel and slash partitions */
+
+ partition@100000 {
+ reg = <0x100000 0x80000>;
+ label = "uboot-env0";
+ };
+
+ partition@180000 {
+ reg = <0x180000 0x80000>;
+ label = "uboot-env1";
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x300000>;
+ label = "reserved";
+ };
+
+ partition@500000 {
+ reg = <0x500000 0x5f00000>;
+ label = "ubi";
+ };
+
+ partition@6500000 {
+ reg = <0x6500000 0x400000>;
+ label = "pool";
+ read-only;
+ };
+
+ partition@6900000 {
+ reg = <0x6900000 0x15e0000>;
+ label = "flash";
+ read-only;
+ };
+
+ partition@7ee0000 {
+ reg = <0x7ee0000 0x20000>;
+ label = "pf";
+ read-only;
+ };
+
+ /* BBT is at the end of the flash - 100000@7f00000 */
+ };
+ };
+ };
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+ i2c@3000 {
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@fc00 {
+ };
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ };
+ };
+
+ enet0: ethernet@b0000 {
+ phy-connection-type = "rgmii-id";
+ phy-handle = <&phy0>;
+ nvmem-cells = <&macaddr_hwinfo_1f822 0>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ enet1: ethernet@b1000 {
+ status = "disabled";
+ };
+
+ enet2: ethernet@b2000 {
+ status = "disabled";
+ };
+
+ usb@22000 {
+ status = "disabled";
+ };
+
+ usb@23000 {
+ status = "disabled";
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ reg = <0 0xffe09000 0 0x1000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = <0 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ system_green: power {
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ default-state = "on";
+ };
+
+ lan {
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ };
+
+ radio1 {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <1>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ radio2 {
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <2>;
+ linux,default-trigger = "phy1tpt";
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset-btn";
+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+/include/ "fsl/p1020si-post.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * HPE MSM460 Board Setup
+ *
+ * Copyright (C) 2022 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ * mpc85xx_rdb.c:
+ * MPC85xx RDB Board Setup
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init msm_pic_init(void)
+{
+ struct mpic *mpic;
+
+ mpic = mpic_alloc(NULL, 0,
+ MPIC_BIG_ENDIAN |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init msm_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("msm_setup_arch()", 0);
+
+ mpc85xx_smp_init();
+
+ fsl_pci_assign_primary();
+
+ pr_info("MSM460 board from HPE\n");
+}
+
+machine_arch_initcall(msm, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init msm_probe(void)
+{
+ if (of_machine_is_compatible("hpe,msm460"))
+ return 1;
+ return 0;
+}
+
+define_machine(msm) {
+ .name = "P1020 RDB",
+ .probe = msm_probe,
+ .setup_arch = msm_setup_arch,
+ .init_IRQ = msm_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
+#endif
+ .get_irq = mpic_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--- /dev/null
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,17 @@ config FIREBOX_T10
+ This board is a VPN Gateway-Router with a
+ Freescale P1010 SoC.
+
++config MSM460
++ bool "HPE MSM460"
++ select DEFAULT_UIMAGE
++ select ARCH_REQUIRE_GPIOLIB
++ select GPIO_MPC8XXX
++ help
++ This option enables support for the HPE MSM460 board.
++
++ This board is a Concurrent Dual-Band wireless access point with a
++ Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ bool "Freescale MPC8540 ADS"
+ select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.
+ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460) += msm460.o
+ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
+ obj-$(CONFIG_P1022_DS) += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
projects / openwrt / staging / blocktrron.git / commitdiff